M32C8A Datasheet, PDF (238/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
17.1.2.1 Baud Rate
In UART mode, the baud rate is the frequency of the clock divided by the setting value of the UiBRG register
(i = 0 to 4) and again divided by 16. Table 17.5 lists an example of baud rate setting.
UiBRG register count source
Actual baud rate = _{16 × (UiBRG register setting value + 1)}
Table 17.5 Baud Rate
Target
Baud Rate
(bps)
UiBRG
Count
Source
Peripheral Clock: 16MHz
Peripheral Clock: 24MHz
Peripheral Clock: 32MHz
UiBRG
Actual Baud
UiBRG
Actual Baud
UiBRG
Actual Baud
Setting Value:
Rate
Setting Value:
Rate
Setting Value:
Rate
n
(bps)
n
(bps)
n
(bps)
1200 f8
103(67h)
1202
155(9Bh)
1202
207(CFh)
1202
2400 f8
51(33h)
2404
77(4Dh)
2404
103(67h)
2404
4800 f8
25(19h)
4808
38(26h)
4808
51(33h)
4808
9600 f1
103(67h)
9615
155(9Bh)
9615
207(CFh)
9615
14400 f1
68(44h)
14493
103(67h)
14423
138(8Ah)
14388
19200 f1
51(33h)
19231
77(4Dh)
19231
103(67h)
19231
28800 f1
34(22h)
28571
51(33h)
28846
68(44h)
28986
31250 f1
31(1Fh)
31250
47(2Fh)
31250
63(3Fh)
31250
38400 f1
25(19h)
38462
38(26h)
38462
51(33h)
38462
51200 f1
19(13h)
50000
28(1Ch)
51724
38(26h)
51282
17.1.2.2 LSB First or MSB First
As shown in Figure 17.20, the UFORM bit in the UiC0 register (i = 0 to 4) determines a bit order. This function
can be used when data length is 8 bits long.
(1) When the UFORM bit in the UiC0 register (i = 0 to 4) is set to 0 (LSB first)
"H"
TXDi
"L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
"H"
RXDi
"L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the UFORM bit is set to 1 (MSB first)
"H"
TXDi
"L"
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
"H"
RXDi
"L"
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
The above applies under the following conditions:
- UiC0 register: CKPOL bit = 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock)
- UiC1 register: UiLCH bit = 0 (not inverted) and the UiLCH bit in the UiC1 register is set to 0 (not inverted).
ST: Start bit
P: Parity bit
SP: Stop bit
Figure 17.20 Bit Order
Rev.1.00 Jul 15, 2007 Page 221 of 352
REJ09B0385-0100