M32C8A Datasheet, PDF (87/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
9. Clock Generation Circuits
Interrupt request level
determination output
Vdet4 detection
interrupt signal
NMI
RESET
PM21
Logic 1 write signal
to CM10 bit
CM10
Stop mode
SQ
R
S
WAIT instruction R Q
CM02
Clock stop signal in wait mode
Main clock oscillation circuit
XIN XOUT
fXIND
Software reset
Watchdog timer reset
Hardware reset 2
CM05
CM21
Stop mode
CM05
Stop mode
PM26
Clock stop signal
in wait mode
PM22
PM26
PM27
CM21
Stop mode
Sub clock oscillation circuit
XCIN XCOUT
Reset the
Main clock
CM17
0
CM21
0
divider (divide-
by-8 mode)
1
PLL frequency
1
synthesizer _fPLL
Clock stop signal
in wait mode
Divider
0
(divide-by-m)
MCD register⁽²⁾
1
CM07
Peripheral function
clock source: fPFC
On-chip fROC
fAD
oscillator
f1
Enable oscillation
Clock stop signal
in wait mode
VC27
f8
1/8 1/4
f32
00
fXIND ⁰¹
CST
fROC ₁₀
PM27～ PM26
1/2n
f2n⁽¹⁾
fC
CM04
1/32 fC32
CPSR=1
Reset the divider
Oscillation stop detection circuit
CPU clock
(bus clock)
fCPU
Main clock
Clock edge detect/
charge and discharge
circuit control
Charge and
discharge circuit
Oscillation stop detection
interrupt request
generation circuit
Watchdog timer
interrupt request signal
Vdet4 detection
interrupt request signal
Oscillation stop detection
interrupt request
(non-maskable interrupt requst)
CM21
PLL frequency synthesizer
VCO clock (fVCO)
Main clock
Programmable
counter
Reference
frequency counter
Phase
comparator
Charge
pump
Voltage
controlled
oscillator
(VCO)
1/2
PLL clock (fPLL)
1/3
PLC12
PLC12: bit in the PLC1 register
VC27: bit in the VCR2 register
CM02, CM04, CM05, and CM07: bits in the CM0 register
CM10 and CM17: bits in the CM1 register
CM21: bit in the CM2 regsiter
PM21, PM22, PM26, and PM27: bits in the PM2 register
CST: bit in the TCSPR register
CPSR: bit in the CPSRF register
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. Bits MCD4 to MCD0 in the MCD register select the dividing ratio (divide-by-m mode: m = 1, 2, 3, 4, 6, 8, 10, 12, 14, 16).
Figure 9.1 Clock Generation Circuit
Rev.1.00 Jul 15, 2007 Page 70 of 352
REJ09B0385-0100