M32C8A Datasheet, PDF (114/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
11. Interrupts
11.3 Hardware Interrupts
Special interrupts and peripheral function interrupts are available as hardware interrupts.
11.3.1 Special Interrupts
Special interrupts are non-maskable.
11.3.1.1 NMI Interrupt
The NMI interrupt occurs when a signal applied to the NMI pin changes from high level (“H”) to low level
(“L”). Refer to 11.8 NMI Interrupt for details.
11.3.1.2 Watchdog Timer Interrupt
The watchdog timer interrupt occurs when the watchdog timer counter underflows. Refer to 12. Watchdog
Timer for details.
11.3.1.3 Oscillation Stop Detection Interrupt
The oscillation stop detection interrupt occurs when the MCU detects a loss of the main clock. Refer to 9.
Clock Generation Circuits for details.
11.3.1.4 Vdet4 Detection Interrupt
The Vdet4 detection interrupt occurs when the voltage applied to VCC1 rises above or drops below Vdet4.
Refer to 6.2 Vdet4 Detection Function for details.
11.3.1.5 Single-Step Interrupt
Do not use the single-step interrupt. This is for use with development support tool only.
11.3.1.6 Address Match Interrupt
When the AIERi bit in the AIER register is set to 1 (address match interrupt enabled), the address match
interrupt occurs immediately before executing the instruction stored in the address indicated by the RMADi
register (i = 0 to 7) .
Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur if
a table data or any address other than the starting address of the instruction is set. Refer to 11.10 Address
Match Interrupt for details.
11.3.2 DMACII Transfer Complete Interrupt
The DMACII transfer complete interrupt is generated by the DMACII function. Refer to 14. DMACII for
details.
11.3.3 Peripheral Function Interrupt
The peripheral function interrupt is generated by the on-chip peripheral functions. The peripheral function
interrupts and software interrupt numbers 8 to 43 for the INT instruction use the same interrupt vector table.
The peripheral function interrupt is maskable.
See Tables 11.2 and 11.3 for the peripheral function interrupt sources. Refer to the descriptions of individual
peripheral functions for details.
Rev.1.00 Jul 15, 2007 Page 97 of 352
REJ09B0385-0100