M32C8A Datasheet, PDF (265/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
(1) Transmit operation
Internal transmit
clock
TE bit in the
1
UiC1 register
0
TI bit in the UiC1
1
register
0
“H”
TXDi output
“L”
Parity error signal
sent back from
receiving device
Signal line level⁽²⁾
TC
(note 1) _{Data is transfer from UiTB register}
Data is set in UiTB register
to UARTi transmit shift register
Start bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Parity bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Detect the level in interrupt routine
"L" level is sent back from the SIM card since parity error has occurred
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TXEPT bit in the
1
UiC0 register
0
IR bit in the
1
SiTIC register
0
Set to 0 by an interrupt request acknowledgement or by program
The above applies under the following conditions:
- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)
- UiC1 register: UiIRS bit = 1 (transmit interrupt is generated at the transmit completion)
(2) Receive operation
Internal receive
clock
RE bit in the
1
UiC1 register
0
Transmit
waveform sent by
transmitting device
“H”
TXDi ouput
“L”
TC
Start bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Parity bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
"L" level is sent back from the SIM card since parity error has occurred
Signal line level⁽³⁾
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RI bit in the
1
UiC1 register
0
IR bit in the SiRIC ¹
register
0
Read from the UiRB register
The above applies under the following conditions:
Set to 0 by an interrupt request acknowledgement or by program
- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)
i = 0 to 4
TC
=
16( m+ 1)
fj
fj: f1, f8, f2n⁽⁴⁾
NOTES:
1. Transmit operation is started when UiBRG overflows after data is set in the UiTB register in the indicated timing.
2. Because pins TXDi and RXDi are connected, a composite waveform, consisting of transmit waveform from the TXDi pin and parity error signal from the
receiving device, is generated.
3. Because pins TXDi and RXDi are connected, a composite waveform consisting of transmit waveform from the transmitting device and parity error
signal from the TXDi pin, is generated.
4. Bits CNT3 to CNT0 in the TCSPR register selects no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.33 SIM Interface Operation
Rev.1.00 Jul 15, 2007 Page 248 of 352
REJ09B0385-0100