M32C8A Datasheet, PDF (152/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
14. DMACII
14.1.2 DMACII Index
The DMACII index is an 8- to 32-byte data table, which stores parameters for transfer mode, transfer counter,
source address (or immediate data), operation address as an address to be calculated, destination address, chain
transfer address, and end-of-transfer interrupt address.
The DMACII index must be located on the RAM area.
Figure 14.2 shows a configuration of the DMACII index. Table 14.2 lists an example configuration of the
DMACII index.
Memory-to-Memory Transfer, Immediate Transfer,
Calculation Transfer
16 bits
DMACII Index
Starting Address _{Transfer mode (MOD)}
(BASE)
BASE+2 Transfer counter (COUNT)
Multiple Transfer
16 bits
BASE ^{Transfer mode (MOD)}
BASE+2 Transfer counter (COUNT)
BASE+4 Transfer source address (or immediate data) (SADR)
BASE+4 Transfer source address (SADR1)
BASE+6 Operation address⁽¹⁾ (OADR)
BASE+6 Transfer destination address (DADR1)
BASE+8 Transfer destination address (DADR)
BASE+8 Transfer source address (SADR2)
BASE+10 Chain Transfer Address (lower byte)⁽²⁾ (CADR0)
BASE+10 Transfer destination address (DADR2)
BASE+12 Chain Transfer Address (higher byte)⁽²⁾ (CADR1)
BASE+14 ^{End-of-Transfer Interrupt Address (lower byte)(3)}
(IADR0)
End-of-Transfer Interrupt Address (higher byte)⁽³⁾
BASE+16 _(IADR1)
to
BASE+28 Transfer source address (SADR7)
BASE+30 Transfer destination address (DADR7)
NOTES:
1. This data is not needed unless using the calculation transfer function.
2. This data is not needed unless using the chain transfer function.
3. This data is not needed unless using the end-of-transfer interrupt.
Place the DMACII index in the RAM. Necessary data must be set top-aligned without any space. For example, if not using the
calculation transfer function, assign a transfer destination address to BASE+6.
The starting address of the DMACII index must be assigned to the interrupt vector of the peripheral function interrupt triggering
a DMACII request.
Figure 14.2 DMACII Index
Details of the DMACII index are described below. Set these parameters in the specified order listed in Table
14.2, depending on DMACII transfer mode.
• Transfer mode (MOD)
MOD is two-byte data and required to set transfer mode. Figure 14.3 shows a configuration for transfer mode.
• Transfer counter (COUNT)
COUNT is two-byte data and required to set the number of transfer.
• Transfer source address (SADR)
SADR is two-byte data and required to set a source memory address or immediate data.
• Operation address (OADR)
OADR is two-byte data and required to set a memory address to be calculated. Set this data only when using
the calculation transfer function.
• Transfer destination address (DADR)
DADR is two-byte data and required to set a destination memory address.
• Chain transfer address (CADR)
CADR is four-byte data and required to set the starting address of the DMACII index for the next transfer. Set
this data only when using the chain transfer function.
• End-of-transfer interrupt address (IADR)
IADR is four-byte data and required to set a jump address for end-of-transfer interrupt processing. Set this data
only when using the end-of-transfer interrupt.
The abbreviations shown in parentheses( ) for each parameter are used in this section.
Rev.1.00 Jul 15, 2007 Page 135 of 352
REJ09B0385-0100