M32C8A Datasheet, PDF (116/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
11. Interrupts
11.5 Interrupts and Interrupt Vectors
There are four bytes in each interrupt vector. Set the starting address of an interrupt routine in each interrupt vector.
When an interrupt request is acknowledged, an interrupt routine is executed from the address set in its interrupt
vector. Figure 11.3 shows an interrupt vector.
MSB
LSB
Vector address+0
8 Low-order bits of address
Vector address+1
8 Middle-order bits of address
Vector address+2
8 High-order bits of address
Vector address+3
00h
Figure 11.3 Interrupt Vector
11.5.1 Fixed Vector Table
The fixed vector table is allocated addresses FFFFDCh to FFFFFFh. Table 11.1 lists the fixed vector table.
Table 11.1 Fixed Vector Table
Interrupt
Source
Vector Addresses
Address (L) to Address (H)
Undefined
instruction
FFFFDCh to FFFFDFh
Overflow
FFFFE0h to FFFFE3h
BRK instruction FFFFE4h to FFFFE7h
Address match
−
Watchdog timer
FFFFE8h to FFFFEBh
FFFFECh to FFFFEFh
FFFFF0h to FFFFF3h
−
NMI
Reset
FFFFF4h to FFFFF7h
FFFFF8h to FFFFFBh
FFFFFCh to FFFFFFh
Remarks
Reference
M32C/80 series
software manual
If the content of the address
FFFFE7h is FFh, the CPU
executes from the address
stored into software interrupt
number 0 in the relocatable
vector table.
Reserved space
These addresses are used for
the watchdog timer interrupt,
oscillation stop detection
interrupt, and Vdet4 detection
interrupt.
Reset,
clock generation circuit,
watchdog timer
Reserved space
Reset
11.5.2 Relocatable Vector Table
The relocatable vector table occupies 256 bytes beginning from the address set in the INTB register. Tables
11.2 and 11.3 list the relocatable vector table.
Set an even address to the starting address of the vector set in the INTB register to increase the interrupt
sequence execution rate.
Rev.1.00 Jul 15, 2007 Page 99 of 352
REJ09B0385-0100