M32C8A Datasheet, PDF (327/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.25 Microprocessor Mode
Symbol
Parameter
tac1(RD-DB) Data input access time (RD standard)
tac1(AD-DB)
Data input access time (AD standard, CS standard)
tac2(RD-DB)
tac2(AD-DB)
Data input access time (RD standard, when accessing a space with the
multiplexed bus)
Data input access time (AD standard, when accessing a space with the
multiplexed bus)
tsu(DB-BCLK) Data input setup time
tsu(RDY-BCLK) _{RDY input setup time}
tsu(HOLD-BCLK) _{HOLD input setup time}
th(RD-DB)
Data input hold time
th(BCLK-RDY) _{RDY input hold time}
th(BCLK-HOLD) _{HOLD input hold time}
td(BCLK-HLDA) _{HLDA output delay time}
Standard
Unit
Min.
Max.
(note 1) _ns
(note 1) _ns
(note 1) _ns
(note 1) _ns
26
ns
26
ns
30
ns
0
ns
0
ns
0
ns
25
ns
NOTE:
1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
10⁹ × m
tac1(RD-DB) =
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) + 1)
f(BCLK) × 2
tac1(AD-DB) =
10⁹ × n
f(BCLK)
- 35 [ns] (if external bus cycle is aφ + bφ, n = a + b)
10⁹ × m
tac2(RD-DB) =
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
f(BCLK) × 2
10⁹ × p
tac2(AD-DB) =
- 35 [ns] (if external bus cycle is aφ + bφ, p = {(a + b - 1) × 2} + 1)
f(BCLK) × 2
Rev.1.00 Jul 15, 2007 Page 310 of 352
REJ09B0385-0100