M32C8A Datasheet, PDF (71/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
8. Bus
8.2.3 Read/Write Output Signals
When using a 16-bit data bus, the PM02 bit in the PM0 register selects either a combination of the “RD, WR,
and BHE” outputs or the “RD, WRL, and WRH” outputs to determine the read/write output signals. When the
DS3 to DS0 in the DS register are set to 0 (8-bit external data bus width), set the PM02 bit to 0 (RD/WR/BHE).
When any of the DS3 to DS0 bits are set to 1 (16-bit external data bus width) to access an 8-bit space, the
combination of “RD, WR, and BHE” is automatically selected regardless of the PM02 bit setting. Table 8.4
lists RD, WRL, and WRH outputs. Table 8.5 list RD, WR, and BHE outputs.
The RD, WR, and BHE outputs are selected for the read/write output signals after reset. When changing to
“RD, WRL, and WRH” outputs, set the PM02 bit first to write data to an external memory.
Table 8.4 RD, WRL, and WRH Outputs
Data Bus Width RD
16 bits
L
H
H
H
8 bits
H
L
WRL
H
L
H
L
L⁽¹⁾
H⁽¹⁾
WRH
H
H
L
L
Not used
Not used
NOTE:
1. These become WR output.
A0
CPU Processing on External Space
Not used Read data
Not used Write 1-byte data to even address
Not used Write 1-byte data to odd address
Not used Write data to both even and odd addresses
H/L Write 1-byte data
H/L Read 1-byte data
Table 8.5 RD, WR, and BHE Outputs
Data Bus Width RD
16 bits
H
L
WR
BHE
L
L
H
L
H
L
H
L
H
H
H
L
L
8 bits
L
H
L
H
L
Not used
L
H
Not used
A0
CPU Processing on External Space
H
Write 1-byte data to odd address
H
Read 1-byte data from odd address
L
Write 1-byte data to even address
L
Read 1-byte data from even address
L
Write data to both even and odd addresses
L
Read data from both even and odd addresses
H/L Write 1-byte data
H/L Read 1-byte data
Rev.1.00 Jul 15, 2007 Page 54 of 352
REJ09B0385-0100