M32C8A Datasheet, PDF (247/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
(1) When the IICM2 bit is set to 0 (ACK or NACK interrupt) and the CKPH bit is set to 0 (no clock delay)
SCLi
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK,NACK)
ACK interrupt (DMA request) or
NACK interrupt
Transferred to the UiRB register
b15
b9 b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
Contents of the UiRB register
(2) When the IICM2 bit is set to 0 and the CKPH bit is set to 1 (clock delay)
SCLi
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA request) or
NACK interrupt
Transferred to the UiRB register
b15
b9 b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
Contents of the UiRB register
(3)When the IICM2 bit is set to 1 (UART transmit or receive interrupt) and the CKPH bit is set to 0
SCLi
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK,NACK)
Receive interrupt
(DMA request)
Transmit interrupt
Transferred to the UiRB register
b15
b9 b8 b7
b0
D0 − D7 D6 D5 D4 D3 D2 D1
Contents of the UiRB register
(4) When the IICM2 bit is set to 1 and the CKPH bit is set to 1
SCLi
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt
(DMA request)
Transmit interrupt
Transferred to the UiRB register (first time)
b15
b9 b8 b7
b0
D0 − D7 D6 D5 D4 D3 D2 D1
Contents of the UiRB register
Transferred to the UiRB register
(second time)
b15
b9 b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
Contents of the UiRB register
i = 0 to 4
The above applies when the CKDIR bit in UiMR register = 1 (external clock selected)
Figure 17.24 Transfer Timing to the UiRB Register and Interrupt Timing
Rev.1.00 Jul 15, 2007 Page 230 of 352
REJ09B0385-0100