M32C8A Datasheet, PDF (100/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
9. Clock Generation Circuits
9.2 CPU Clock and BCLK
The CPU clock is used to operate the CPU and also used as the count source for the watchdog timer. After reset,
the CPU clock is the main clock divided by eight. The bus clock (BCLK) has the same frequency as the CPU clock
and can be output from the BCLK pin in microprocessor mode. Refer to 9.4 Clock Output Function for details.
The main clock, sub clock, on-chip oscillator clock, or PLL clock can be selected as the clock source for the CPU
clock.
When the main clock, on-chip oscillator clock, or PLL clock is selected as the clock source for the CPU clock, the
selected clock source divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 becomes the CPU clock. Bits MCD4
to MCD0 in the MCD register select the clock division. When the MCU enters stop mode or low-power
consumption mode, bits MCD4 to MCD0 are set to 01000b (divide-by-8 mode). Therefore, when the CPU clock
source is switched to the main clock next time, the CPU clock is the main clock divided by eight. Refer to 9.5
Power Consumption Control for details.
9.3 Peripheral Function Clock
The peripheral function clocks are used to operate the peripheral functions excluding the watchdog timer. The
clock selected by the CM17 bit in the CM1 register and the CM21 bit in the CM2 register (any of the main clock,
PLL clock, or on-chip oscillator clock) becomes the peripheral function clock source (fPFC).
9.3.1 f1, f8, f32, and f2n
f1, f8 and f32 are fPFC divided by 1, 8, or 32.
Bits PM27 and PM 26 in the PM2 register select a f2n clock source from fPFC, XIN clock (fXIND), and the on-
chip oscillator clock (fROC). Bits CNT3 to CNT0 in the TCSPR register select a f2n division. (n = 1 to 15. No
division when n = 0.)
When wait mode is entered while the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait
mode) or when the CM05 bit is set to 1 using the main clock as the peripheral function clock source, fPFC
stops. When bits PM27 and PM26 in the PM2 register are set to 10b (on-chip oscillator is selected for the f2n
clock source), f2n does not stop in wait mode.
f1, f8, and f2n are used to operate the serial interface and also is used as the count source for timer A and
timer B.
The CLKOUT pin outputs f8 and f32. Refer to 9.4 Clock Output Function for details.
9.3.2 fAD
fAD is used to operate the A/D converter and has the same frequency as fPFC.
When wait mode is entered while the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait
mode) or when the CM05 bit is set to 1 using the main clock as the peripheral function clock source, fAD stops.
9.3.3 fC32
fC32 is the sub clock divided by 32. fC32 is used as the count source for timer A and timer B. fC32 is available
if the sub clock is running.
Rev.1.00 Jul 15, 2007 Page 83 of 352
REJ09B0385-0100