M32C8A Datasheet, PDF (267/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
17.1.6.2 Formats
17.1.6.2.1 Direct Format
When data is transmitted, data set in the UiTB register (i = 0 to 4) is transmitted with even parity, starting from
D0. When data is received, received data is stored into the UiRB register, starting from D0. A parity error is
determined with even parity.
Set the bits as follows to transmit or receive in the direct format.
• Set the PRYE bit in the UiMR register to 1 (parity enabled).
• Set the PRY bit in the UiMR register to 1 (even parity).
• Set the UFORM bit in the UiC0 register to 0 (LSB first).
• Set the UiLCH bit in the UiC1 register to 0 (not inverted).
17.1.6.2.2 Inverse Format
When data is transmitted, values set in the UiTB register are logically inverted. The data with the inverted
values is transmitted with odd parity, starting from D7. When data is received, received data is logically
inverted to be stored into the UiRB register, starting from D7. A parity error is determined with odd parity.
Set the bits as follows to transmit or receive in the inverse format.
• Set the PRYE bit to 1 (parity enabled).
• Set the PRY bit to 0 (odd parity).
• Set the UFORM bit to 1 (MSB first).
• Set the UiLCH bit to 1 (inverted).
(1) Direct format
"H"
TXDi
"L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P: Even parity
P
SP
(2) Inverse format
"H"
TXDi
"L"
i = 0 to 4
ST
D7
D6
D5
D4
D3
D2
D1
D0
P: Odd parity
P
SP
ST: Start bit
SP: Stop bit
Figure 17.36 SIM Interface Formats
Rev.1.00 Jul 15, 2007 Page 250 of 352
REJ09B0385-0100