M32C8A Datasheet, PDF (146/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
13. DMAC
Start
Set the peripheral function
used as DMAi request source
DMD1 register: bits MD21 and MD20 = 00b
bits MD31 and MD30 = 00b
DMiSL register: bits DSEL4 to DSEL0
DSR bit = 0
DRQ bit = 1
B flag = 1
DMA2 (A0) register or DMA3 (A1) register
DSA2 (SB) register or DSA3 (FB) register
<When using repeat transfer>
DRA2 (SVP) register or DRA3 (VCT) register
Set the control registers of the peripheral function,
but do not yet start.
DMA disabled for channel 2
DMA disabled for channel 3
Write with LDC instruction
DMA request source select bits
DMA requested
(note 1)
Select register bank 1⁽²⁾
Set an incremented source address or
incremented destination address
Set a fixed source address or
fixed destination address
Write with MOV instruction
Write with LDC instruction
Set an incremented source address or
incremented destination address
Write with LDC instruction
DCT2 (R0) register or DCT3 (R1) register
<When using repeat transfer>
DRC2 (R2) register or DRC3 (R3) register
Set the number of transfer⁽³⁾
Set the number of transfer, which is to be
reloaded
Write with MOV instruction
Write with MOV instruction
B flag = 0
Select register bank 0⁽²⁾
DMD1 register: bits MD21 and MD20
BW2 bit
RW2 bit
bits MD31 and MD30
BW3 bit
RW3 bit
Start the peripheral function
used as DMAi request source
Transfer mode select bits for channel 2
Transfer unit select bit for channel 2
Transfer direction select bit for channel 2
Transfer mode select bits for channel 3
Transfer unit select bit for channel 3
Transfer direction select bit for channel 3
(note 5)
Write with LDC instruction
(note 4)
End
i = 2 and 3
NOTES:
1. When setting the DMiSL register, write a 1 to the DRQ bit.
2. The register bank 1 and high-speed interrupt cannot be used when using DMA2 and DMA3.
3. When the INT interrupts are selected as a DMA request source, do not write a 1 to the DCTi register. If the DCTi register is
1, do not generate a DMA request when writing 01b or 11b to bits MDi1 and MDi0.
4. Wait six CPU clock cycles or more by program to set bits MDi1 and MDi0 to 01b or 11b after setting the DMiSL register.
5. When a DMA transfer is started by the software trigger, set both the DSR and DRQ bit in the DMiSL register to 1 at the
same time.
Figure 13.8 Register Settings When Using DMA2 or DMA3
Rev.1.00 Jul 15, 2007 Page 129 of 352
REJ09B0385-0100