M32C8A Datasheet, PDF (197/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
16. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 0⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC0
Address
0308h
After Reset
00h
Bit Symbol
Bit Name
Function
RW
INV00
INV01
INV02
ICTB2 count condition
select bits
b1 b0
0 0:
0 1: ^{Timer B2 underflow}
RW
1 0: Timer B2 underflow at the rising edge of the
timer A1 reload control signal⁽²⁾
(every odd-numbered timer B2 underflow)
1 1: Timer B2 underflow at the falling edge of the
RW
timer A1 reload control signal⁽²⁾
(every even-numbered timer B2 underflow)
Three-phase motor control timer 0: Three-phase motor control timer function not used
function enable bit⁽³⁾
1: Three-phase motor control timer function used^(4,5)
RW
INV03
Three-phase motor control timer 0: Three-phase motor control timer output disabled^(5,6)
output control bit
1: Three-phase motor control timer output enabled
RW
INV04
Upper and lower arm
0: Simultaneous turn-on enabled
simultaneous turn-on disable bit 1: Simultaneous turn-on disabled
RW
INV05
Upper and lower arm
0: Not detected
simultaneous turn-on detect flag 1: Detected ⁽⁷⁾
RO
INV06
INV07
Modulation mode select bit⁽⁹⁾
Software trigger select bit
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode⁽¹⁰⁾
RW
Transfer trigger is generated when the INV07 bit
is set to 1. Trigger for the dead time timer is also
generated when the INV06 bit is set to 1.
RW
This bit is read as 0.
NOTES:
1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to 1 (write enable). Set bits INV06 and INV02 to INV00
while timers A1,A2, A4, and B2 are stopped.
2. Set the INV01 bit to 1 after setting a value to the ICTB2 register. Also, when the INV01 bit is set to 1, set the timer A1 count start
bit to 1 prior to the first timer B2 underflow.
3. Set pins after the INV02 bit is set to 1. Refer to the table, Pin settings when using three-phase motor control timer function .
4. Set the INV02 bit to 1 to operate the dead time timer, U-, V-, and W-phase output control circuits, and ICTB2 counter.
5. When the INV03 bit is set to 0 and the INV02 bit to 1, pins U, U, V, V, W, and W (including when other output functions are
assiged to these pins) are all placed in high-impedance states.
6. The INV03 bit becomes 0 when one of the following occurs:
-Reset
-The both upper and lower arms output the active level signals at the same time while the INV04 bit is set to 1
-The INV03 bit is set to 0 by program
-Signal applied to the NMI pin changes from "H" to "L" (while an "L" is applied to the NMI pin, the INV03 bit cannot be set to 1).
7. The INV05 bit cannot be set to 1 by program. To set the INV05 bit to 0, write a 0 to the INV04 bit.
Figure 16.2 INVC0 Register
Rev.1.00 Jul 15, 2007 Page 180 of 352
REJ09B0385-0100