M32C8A Datasheet, PDF (364/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
24. Usage Notes
24.10 A/D Converter
• Set the ADST bit to 1 (A/D conversion starts) after setting registers AD0CON0 (ADST bit excluded),
AD0CON1, AD0CON2, AD0CON3, and AD0CON4.
• When the VCUT bit in the AD0CON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for 1 μs or more to start A/D conversion.
Set the VCUT bit to 0 when A/D conversion is not used to reduce power consumption.
• To prevent latch-up and malfunction due to noise and also to minimize a conversion error, insert a capacitor
between the AVSS pin and each of the following pins: the AVCC pin, VREF pin, or analog input pin ANi_j
(i = none, 15; j = 0 to 7). Insert a capacitor between the VCC pin and the VSS pin as well. Figure 24.4 shows
an example of individual pin handling.
VCC1
C4
VCC2
C5
MCU
VCC1
AVCC
VCC1
VSS
VCC2
VSS
VREF
C1
AVSS
ANi
C2
C3
NOTES:
1.C1 ≥ 0.47 μF, C2 ≥ 0.47 μF, C3 ≥ 10000 pF, C4 ≥ 0.1 μF, C5 ≥ 0.1 μF (reference values)
2.Use thick and shortest possible wiring to connect capacitors.
Figure 24.4 Individual Pin Handling
• Set the port direction bit in the PDk register (k = 0 to 15), which corresponds to a pin used as an analog input
pin, to 0 (input mode). Also, set the port direction bit in the PDk register corresponding to the ADTRG pin, to
0 (input mode.)
• When the key input interrupt is used, do not select pins P10_4 to P10_7 (AN_4 to AN_7) as analog input pins.
• φAD frequency must be 16 MHz or lower when VCC1 = 4.2 V to 5.5 V, or 10 MHz or lower when
VCC1 = 3.0 V to 5.5 V. When the sample and hold is not activated, φAD frequency must be 250 kHz or
higher. When the sample and hold is activated, φAD frequency must be 1 MHz or higher.
• When A/D operating mode is changed, set bits CH2 to CH0 in the AD0CON0 register or bits SCAN1 and
SCAN0 in the AD0CON1 register again to select analog input pins.
• The voltage applied to AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, and ANEX1 must be VCC1 or below.
Rev.1.00 Jul 15, 2007 Page 347 of 352
REJ09B0385-0100