M32C8A Datasheet, PDF (177/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
15. Timers (Timer A)
15.1.2.1 Counter Reset by Two-Phase Pulse Signal Processing
The counter value of timer can be set to 0 by a Z-phase pulse signal input (counter reset) when processing
two-phase pulse signals.
This function can be used when all the following conditions are met; timer A3 event counter mode, two-phase
pulse signal processing, free-running count operation type, and multiply-by-4 processing. The Z-phase pulse
signal is applied to the INT2 pin.
When the TAZIE bit in the ONSF register is set to 1 (Z-phase input enabled), Z-phase pulse input is enabled to
reset the counter. To reset the counter by a Z-phase pulse input, set the TA3 register to 0000h beforehand.
A Z-phase pulse input is enabled when the edge of a signal applied to the INT2 pin is detected. The POL bit in
the INT2IC register can determine the edge polarity. The Z-phase pulse must have a pulse width of one timer
A3 count source cycle or more. Figure 15.17 shows relations between two-phase pulses (A-phase and B-phase)
and the Z-phase pulse.
Z-phase pulse input resets the counter in the next count source timing followed a Z-phase pulse input.
A timer A3 interrupt request is generated twice in a row if a timer A3 overflow or underflow, and the counter
reset by an INT2 input occur at the same time. Do not generate a timer A3 interrupt request when this function
is used.
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
INT2⁽¹⁾
(Z phase)
Pulse width of one count source cycle or more is required
Counter value
m
m+1
1
2
3
4
5
6
NOTE:
1. Example when the rising edge of INT2 is selected.
Figure 15.17 Relations between Two-Phase Pulses (A-Phase and B-Phase) and Z-Phase Pulse
Rev.1.00 Jul 15, 2007 Page 160 of 352
REJ09B0385-0100