M32C8A Datasheet, PDF (264/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
Start initial setting
I flag = 0
UiMR register: bits SMD2 to SMD0 = 101b
CKDIR bit = 0
STPS bit = 0
PRY bit
PRYE bit = 1
IOPOL bit = 0
UiSMR register = 00h
UiSMR2 register = 00h
UiSMR3 register = 00h
UiSMR4 register = 00h
UiC0 register: bits CLK1 and CLK0
CRD bit = 1
NCH bit = 1
CKPOL bit = 0
UFORM bit
UiBRG register = m
UiC1 register: TE bit = 0
RE bit = 0
UiIRS bit = 1
UiRRM bit = 0
UiLCH bit
UiERE bit = 1
SiTIC register: bits ILVL2 to ILVL0
IR bit = 0
SiRIC register: bits ILVL2 to ILVL0
IR bit = 0
Pin setting in the Function Select Registers
I flag = 1
UiC1 register: TE bit = 1
RE bit = 1
End initial setting
Interrupt disabled
UART mode: 8-bit data length
Select internal clock
Select 1 stop bit
Parity select bit⁽¹⁾
Parity enabled
UiBRG register count source select bits
CTS function disabled
N-channel open drain output
Bit order select bit⁽²⁾
m = 00h to FFh Baud rate =
fj
16(m + 1)
fj = f1, f8, f2n⁽³⁾
Transmit operation disabled
Receive operation disabled
Transmit completion as transmit interrupt source
Data logic select bit⁽²⁾
Error signal output enabled
Transmit interrupt priority level select bits
Interrupt not requested
Receive interrupt priority level select bits
Interrupt not requested
Interrupt enabled
Transmit operation enabled
Receive operation enabled
Transmit operation starts by writing data to the UiTB register
Receive operation starts when the start bit is detected.
Read the UiRB register when the receive operation is completed.
i = 0 to 4
NOTES:
1. Set to 1 in the direct format, and set to 0 in the inverse format.
2. Set to 0 in the direct format, and set to 1 in the inverse format.
3. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
4. Determine whether an "L" is output from the TXDi pin by reading the port that shares a pin with the RXDi pin in the reception
complete interrupt routine. When an "L" is output, wait for one clock cycle to read the UiRB register.
Figure 17.32 Register Settings in SIM Mode
Rev.1.00 Jul 15, 2007 Page 247 of 352
REJ09B0385-0100