M32C8A Datasheet, PDF (174/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
15. Timers (Timer A)
FFFFh
n
Contents of the counter
n = contents of the reload
register
Count starts
Overflow
Count resumes
Decrement to increment
Underflow
Count stops
Reload
Reload
Input to TAiIN pin
TAiS bit in the
TABSR register
TAiUD bit in the
UDF register
IR bit in the TAiIC
register
i = 0 to 4
0000h
“H”
“L”
1
0
1
0
1
0
Set to 1 by program
Set to 0 by an interrupt request acknowledgement or by program
(Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 01b (event counter mode)
The MR1 bit is set to 1 (rising edges of an external signal counted)
The MR2 bit is set to 0 (UDF register setting)
Bits TCK1 to TCK0 bit are set to 00b (reload)
Figure 15.15 Operation in Event Counter Mode When Not Handling Two-Phase Pulse Signals
Rev.1.00 Jul 15, 2007 Page 157 of 352
REJ09B0385-0100