M32C8A Datasheet, PDF(186/372 Page) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

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M32C8A Datasheet, PDF (186/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

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M32C/8A Group

15. Timers (Timer B)

Timer Bi Mode Register (i = 0 to 5)

(Pulse Period Measurement Mode, Pulse Width Measurement Mode)

b7 b6 b5 b4 b3 b2 b1 b0

10

Symbol

TB0MR to TB5MR

Address

035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh

After Reset

00XX 0000b

Bit Symbol

Bit Name

Function

RW

TMOD0

RW

b1 b0

Operating mode select bits

1 0: Pulse period measurement mode

TMOD1

Pulse width measurement mode

RW

MR0

b3 b2

RW

Measurement mode

select bits(1)

0 0: Pulse period measurement 1

0 1: Pulse period measurement 2

1 0: Pulse width measurement

MR1

1 1: Do not set to this value

RW

Registers TB0MR and TB3MR:

Set to 0 in pulse period measurement mode, pulse width measurement mode.

RW

MR2

Registers TB1MR, TB2MR, TB4MR, and TB5MR:

Unimplemented.

â

Write 0. Read as undefined value.

MR3

Timer Bi overflow flag(2)

0: No overflow has occurred

1: Overflow has occurred(3)

RO

TCK0

b7 b6

RW

0 0: f1

Count source select bits

0 1: f8

1 0: f2n(4)

TCK1

1 1: fC32

RW

NOTES:

1. Bits MR1 and MR0 determine the following measurement modes:

Pulse period measurement 1 (bits MR1 and MR0 are set to 00b):

Measures the width between the falling edges of a pulse

Pulse period measurement 2 (bits MR1 and MR0 bits are set to 01b):

Measures the width between the rising edges of a pulse

Pulse width measurement (bits MR1 and MR0 bits are set to 10b):

Measures the width between a falling edge and a rising edge of a pulse, and between a rising edge and a falling edge of a pulse

2. The MR3 bit is undefined when reset.

3. To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write a 0 to the TBiMR register after the MR3 bit

becomes 1 (overflow), while the TBiS bit in TABSR or TBSR register is set to 1 (count starts).

4. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the

TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.

Figure 15.24 TB0MR to TB5MR Registers in Pulse Period Measurement Mode, Pulse Width

Measurement Mode

Rev.1.00 Jul 15, 2007 Page 169 of 352

REJ09B0385-0100

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