M32C8A Datasheet, PDF (83/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
8. Bus
8.3 Page Mode Control Function
The page mode control function allows high-speed read access to the external memory compatible with the page
mode control. While the MCU accesses data within the eight-byte block of consecutive addresses which have the
same 21 high-order bits, less cycles are required for the subsequent bus accesses than the first bus access.
The EWCRi register (i = 0 to 3) determines how many wait states are inserted for the first bus access. Registers
PWCR0 and PWCR1 determine how many wait states are inserted for the subsequent bus accesses. Use the
following procedure to enable the page mode control.
(1) Set bits EWCRi4 to EWCRi0 in the EWCRi register.
(2) Set bits PWCRj02 to PWCRj00 and bits PWCRj06 to PWCRj04 in the PWCRj register (j = 0, 1).
(3) Set bits PWCRj03 and PWCRj07 to 1 (page mode control enabled).
When using the page mode control function, access all the external spaces using page mode control. It is not
allowed to combine the page mode controlled access and the normal access to external spaces.
Set bits PM05 and PM04 to 00b (multiplexed bus is not used). The page mode control function and multiplexed
bus cannot be used at the same time.
Figure 8.12 and 8.13 show registers PWCR0 and PWCR1. Figure 8.14 shows a diagram of external bus timing with
page mode function.
Page Mode Wait Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PWCR0
Address
004Ch
After Reset
0001 0001b
Bit Symbol
Bit Name
Function
RW
PWCR000
External space 0
PWCR001
subsequent access
wait select bits
PWCR002
b2 b1 b0
RW
0 0 1: 1φ + 1φ
0 1 0: 1φ + 2φ
0 1 1: 1φ + 3φ
RW
1 0 0: 1φ + 4φ
Do not set to values other than the above.
RW
PWCR003
External space 0
page mode control enable bit
0: Page mode control disabled
1: Page mode control enabled⁽¹⁾
RW
PWCR004
External space 1
PWCR005
subsequent access
wait select bits
PWCR006
b6 b5 b4
RW
0 0 1: 1φ + 1φ
0 1 0: 1φ + 2φ
0 1 1: 1φ + 3φ
RW
1 0 0: 1φ + 4φ
Do not set to values other than the above.
RW
PWCR007
External space 1
page mode control enable bit
0: Page mode control disabled
1: Page mode control enabled⁽¹⁾
RW
NOTE:
1. When page mode control is enabled, set the EWCRi6 bit in the EWCRi register (i = 0 to 3) to 0 (add no recovery
cycle when accessing external space i ).
Figure 8.12 PWCR0 Register
Rev.1.00 Jul 15, 2007 Page 66 of 352
REJ09B0385-0100