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M32C8A Datasheet, PDF (142/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series
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M32C/8A Group
13. DMAC
DMAi Memory Address Reload Register(1) (i = 0 to 3)
b23 b16 b15 b8 b7 b0
Symbol
DRA0
DRA1
DRA2 (SVP)(2)
DRA3 (VCT)(3)
Address
(CPU internal register)
(CPU internal register)
(CPU internal register)
(CPU internal register)
After Reset
XXXXXXh
XXXXXXh
XXXXXXh
XXXXXXh
Function
Set an incremented source address or incremented destination
address
NOTES:
1. Use the LDC instruction to set registers DRA0 to DRA3.
2. To set the DRA2 register, write to the SVP register.
3. To set the DRA3 register, write to the VCT register.
Setting Range
RW
000000h to FFFFFFh
(16 Mbytes)
RW
DMAi Transfer Count Register (i = 0 to 3)
b15
b8 b7
b0
Symbol
DCT0(2)
DCT1(2)
DCT2 (bank1:R0)(3)
DCT3 (bank1:R1)(4)
Address
(CPU internal register)
(CPU internal register)
(CPU internal register)
(CPU internal register)
After Reset
XXXXh
XXXXh
0000h
0000h
Function
Set the number of transfers
Setting Range
RW
0000h to FFFFh(1)
RW
NOTES:
1. When the DCTi register is set to 0000h, no data transfer occurs regardless of a DMA request generation.
2. Use the LDC instruction to set registers DCT0 and DCT1.
3. To set the DCT2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R0 register.
4. To set the DCT3 register, set the B flag to 1 and write to the R1 register.
DMAi Transfer Count Reload Register (i = 0 to 3)
b15
b8 b7
b0
Symbol
DRC0(1)
DRC1(1)
DRC2 (bank1:R2)(2)
DRC3 (bank1:R3)(3)
Address
(CPU internal register)
(CPU internal register)
(CPU internal register)
(CPU internal register)
Function
Set the number of transfers
After Reset
XXXXh
XXXXh
0000h
0000h
Setting Range
RW
0000h to FFFFh
RW
NOTES:
1. Use the LDC instruction to set registers DRC0 and DRC1.
2. To set the DRC2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R2 register.
3. To set the DRC3 register, set the B flag to 1 and write to the R3 register.
Figure 13.4 DRA0 to DRA3 Registers, DCT0 to DCT3 Registers, DRC0 to DRC3 Registers
Rev.1.00 Jul 15, 2007 Page 125 of 352
REJ09B0385-0100
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