M32C8A Datasheet, PDF (158/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
15. Timers
15. Timers
The M32C/8A Group has eleven 16-bit timers, and they are separated into five timer A and six timer B based on their
functions. Individual timers function independently. The count source for each timer is used to operate the timer for
counting and reloading, etc.
Figures 15.1 and 15.2 show block diagrams of timer A and timer B configurations.
f1 f8 f2n fC32
XCIN
Clock Prescaler
1/32
Set the CPSR bit in the
CPSRF register to 1
Reset
TA0IN
TA1IN
TA2IN
TA3IN
TA4IN
TCK1 and TCK0
00
01
10
11
Noise
filter
TCK1 and TCK0
00
01
10
11
Noise
filter
00 ^{TCK1 and TCK0}
01
10
11
Noise
filter
TCK1 and TCK0
00
01
10
11
Noise
filter
TCK1 and TCK0
00
01
10
11
Noise
filter
TMOD1 and TMOD0
00: Timer mode
10: One-shot timer mode
10
11: PWM mode
01
00
01: Event counter mode
11 TA0TGH and TA0TGL
TMOD1 and TMOD0
00: Timer mode
10: One-shot timer mode
10
11: PWM mode
01
00
01: Event counter mode
11 _{TA1TGH and TA1TGL}
TMOD1 and TMOD0
00: Timer mode
10: One-shot timer mode
10
11: PWM mode
01
00
01: Event counter mode
11 TA2TGH and TA2TGL
TMOD1 and TMOD0
00: Timer mode
10: One-shot timer mode
10
11: PWM mode
01
00
01: Event counter mode
11 _{TA3TGH and TA3TGL}
TMOD1 and TMOD0
00: Timer mode
10
10: One-shot timer mode
11: PWM mode
01
00
01: Event counter mode
11 _{TA4TGH and TA4TGL}
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B2 overflow
or underflow signal
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TAiMR register
TAiGH, TAiGL: Bits in the ONSF register or the TRGSR register (i = 0 to 4)
Figure 15.1 Timer A Configuration
fC32
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Rev.1.00 Jul 15, 2007 Page 141 of 352
REJ09B0385-0100