M32C8A Datasheet, PDF (133/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
12. Watchdog Timer
12. Watchdog Timer
The watchdog timer is used to detect the program running improperly. The watchdog timer contains a 15-bit free-
running counter. If a write to the WDTS register is not performed due to a program running out of control, the free-
running counter underflows, which results in the watchdog timer interrupt generation or the MCU reset. When
operating the watchdog timer, write to the WDTS register in a shorter cycle than the watchdog timer cycle in such as
the main routine.
Tables 12.1 and 12.2 list specifications of the watchdog timer. Figure 12.1 shows a block diagram of the watchdog
timer. Figures 12.2 and 12.3 show registers associated with the watchdog timer.
Table 12.1 Watchdog Timer Specifications (1)
Items
Count operation
Count start condition
When underflows
After underflows
Read from watchdog timer
Specifications
The free-running counter decrements
Writing to the WDTS register:
A write to the WDTS register initializes a free-running counter and the counter
decrements from 7FFFh
One of the following occurs (selectable using the CM06 bit in the CM0 register):
• Watchdog timer interrupt generation⁽¹⁾
• MCU reset
The counter continues decrementing
(when the watchdog timer interrupt is selected)
A read from bit 4 to bit 0 in the WDC register returns bit 14 to bit 10 of the free-running
counter
NOTE:
1. The watchdog timer shares the same vector with the oscillation stop detection interrupt and Vdet4 detection
interrupt. When using the watchdog timer interrupt simultaneously with these interrupts, determine whether the
watchdog timer interrupt is generated by reading the D43 bit in the D4INT register in the interrupt rouine.
Table 12.2 Watchdog Timer Specifications (2)
Item
PM22 bit in PM2 register⁽¹⁾
CM07 bit in CM0 register
WDC7 bit in WDC register
Clock source
Prescaler
Count source for counter
Bit Setting and Specifications
0
0
0
0
0
1
1
0
−
CPU clock
Clock divided by MCD register
Sub clock
Divide-by-16
Divide-by-128
Divide-by-2
1
fCPU
× 16
1
fCPU ^{× 128}
1
fCPU
×
2
1
−
−
On-chip oscillator
not available
1
fROC
Time-out period (formula)⁽²⁾
1
fCPU
× 524288
1
fCPU ^{× 4194304}
1
fCPU
× 65536
1
fROC ^{× 32768}
Time-out period (reference)
Operation in wait mode,
stop mode, and hold state
Approx. 16.4 ms
fCPU = 32 MHz
Approx. 131.1 ms
fCPU = 32 MHz
Stops
Approx. 2 s
fCPU = 32 kHz
Approx. 32.8 ms
fROC = 1 MHz
Operates⁽³⁾
−: either 0 or 1
fCPU: CPU clock frequency
fROC: On-chip oscillator clock frequency
NOTES:
1. Once the PM22 bit is set to 1, it cannot be set to 0 by program.
2. Difference between the calculation result and actual period can be one count source cycle of the counter.
3. A write to the CM10 bit in the CM1 register is disabled. Writing a 1 has no effect and the MCU does not enter
stop mode. The watchdog timer interrupt cannot be used to exit wait mode.
Rev.1.00 Jul 15, 2007 Page 116 of 352
REJ09B0385-0100