M32C8A Datasheet, PDF (183/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
15. Timers (Timer B)
15.2 Timer B
Timer B contains the following three modes. Bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 5)
determine which mode is used.
• Timer mode: The timer counts the internal count source.
• Event counter mode: The timer counts overflows/underflows of another timer, or the external pulses.
• Pulse period measurement mode, pulse width measurement mode: The timer measures the pulse period or
pulse width of the external signal.
Figure 15.21 shows a block diagram of timer B. Figures 15.22 to 15.26 show the registers associated with timer B.
Table 15.8 shows TBiIN pin settings (i = 0 to 5).
Clock source select
TCK1 and TCK0
f1 ⁰⁰
f8 ⁰¹
f2n^{(1) 10}
fC32 11
TBj overflow⁽²⁾
TBiIN
Polarity switching
and edge pulse
TCK1
1
0
TMOD1 and TMOD0
00: Timer mode
10: Pulse period and pulse
width measurement mode
01: Event counter mode
TBiS
High-order bits of data bus
Low-order bits of data bus
8 low-order
bits
Reload register
8 high-order
bits
Counter
Counter reset circuit
i= 0 to 5
j = i - 1, except j = 2 if i = 0, j = 5 if i = 3.
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or
divide-by-2n (n = 1 to 15).
2. Overflow signal or underflow signal.
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register
TBiS: Bit in the TABSR register or the TBSR register
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
Addresses
0351h 0350h
0353h 0352h
0355h 0354h
0311h 0310h
0313h 0312h
0315h 0314h
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
Figure 15.21 Timer B Block Diagram
Rev.1.00 Jul 15, 2007 Page 166 of 352
REJ09B0385-0100