M32C8A Datasheet, PDF (334/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
23. Electrical Characteristics
Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
Read Timing (2φ + 2φ Bus Cycle)
VCC1=VCC2=5V
BCLK
ALE
CSi
td(BCLK-ALE)
18ns.max
td(BCLK-CS)
18ns.max
td(AD-ALE)⁽¹⁾
th(BCLK-ALE)
-2ns.min
th(ALE-AD)⁽¹⁾
th(BCLK-CS)
tcyc
-3ns.min
th(RD-CS)⁽¹⁾
tsu(DB-BCLK) 26ns.min
ADi /DBi
ADi
BHE
td(BCLK-AD)
18ns.max
Address
tdz(RD-AD)
8ns.max
tac2(RD-DB)⁽¹⁾
Data input
Address
th(RD-DB) 0ns.min
th(BCLK-AD)
-3ns.min
tac2(AD-DB)⁽¹⁾
th(RD-AD)⁽¹⁾
RD
td(BCLK-RD)
18ns.max
th(BCLK-RD)
-5ns.min
NOTES:
1. Varies with operation frequency:
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle aφ + bφ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle aφ + bφ, n = a)
th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min
tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle aφ + bφ, m = (b x 2) - 1)
tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle aφ + bφ, p = {(a + b - 1) x 2} + 1)
Write Timing (2φ + 2φ Bus Cycle)
BCLK
ALE
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
18ns.max
CSi
tcyc
th(WR-CS)⁽²⁾
th(BCLK-CS)
-3ns.min
td(AD-ALE)⁽²⁾
th(ALE-AD)⁽²⁾
ADi /DBi
Address
Data output
Address
ADi
BHE
td(BCLK-AD)
18ns.max
td(DB-WR)⁽²⁾
th(WR-DB)⁽²⁾
th(BCLK-AD)
-3ns.min
WR,WRL,WRH
td(BCLK-WR)
18ns.max
th(BCLK-WR)
-5ns.min
th(WR-AD)⁽²⁾
NOTES:
1. Varies with operation frequency:
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle aφ + bφ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle aφ + bφ, n = a)
th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min
th(WR-DB) = (tcyc / 2 - 10) ns.min
td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle aφ + bφ, m = (b x 2) - 1)
tcyc=
10⁹
f(BCLK)
Measurement Conditions:
- VCC1 = VCC2 = 4.2 to 5.5 V
- Input high and low voltage VIH = 2.5 V, VIL = 0.8 V
- Output high and low voltage VOH = 2.0 V, VOL = 0.8 V
Figure 23.6 VCC1 = VCC2 = 5 V Timing Diagram (4)
Rev.1.00 Jul 15, 2007 Page 317 of 352
REJ09B0385-0100