M32C8A Datasheet, PDF (88/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
9. Clock Generation Circuits
System Clock Control Register 0⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
0006h
After Reset
0000 1000b
Bit Symbol
Bit Name
Function
RW
CM00
b1 b0
0 0: I/O port P5_3⁽²⁾
RW
Clock output function select bits^{(2) 0 1: Outputs fC}
CM01
1 0: Outputs f8
1 1: Outputs f32
RW
CM02
Peripheral function clock stop in
wait mode bit⁽⁹⁾
0: Peripheral clocks do not stop in wait mode
1: Peripheral clocks stop in wait mode⁽³⁾
RW
CM03
XCIN-XCOUT drive capability
select bit⁽¹⁰⁾
0: Low
1: High
RW
CM04
Port XC switch bit
0: I/O port function
1: XCIN-XCOUT oscillation function⁽⁴⁾
RW
CM05
Main clock (XIN-XOUT)
stop bit^{(5, 9)}
0: Main clock oscillates
1: Main clock stops⁽⁶⁾
RW
CM06
Watchdog timer
function select bit
CM07
CPU clock select bit 0^{(8, 9)}
0: Watchdog timer interrupt
1: Reset⁽⁷⁾
RW
0: Clock selected by the CM21 bit divided by
the MCD register
RW
1: Sub clock
NOTES:
1. Set the CM0 register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. The BCLK, ALE, or "L" signal is output from the P5_3 pin in microprocessor mode. The P5_3 does not function as an I/O port.
3. fC32 does not stop running.
4. To set the CM04 bit to 1, set bits PD8_7 and PD8_6 in the PD8 register to 00b (ports P8_6 and P8_7 in input mode) and the
PU25 bit in the PUR2 register to 0 (no pull-up).
5. The CM05 bit stops the main clock oscillation when entering low-power consumption mode or on-chip oscillator low-power
consumption mode. The CM05 bit cannot be used to determine whether the main clock stops or not. To stop the main clock
oscillation, set the PLC07 bit in the PLC0 register to 0 and the CM05 bit to 1 after setting the CM07 bit to 1 or setting the CM21
bit in the CM2 register to 1 (on-chip oscillator clock).
When the CM05 bit is set to 1, the XOUT pin outputs "H". Since an on-chip feedback resistor remains ON, the XIN pin is pulled
up to the XOUT pin via the feedback resistor.
6. When the CM05 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). In on-chip
oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit is set to 1.
7. Once the CM06 bit is set to 1, it cannot be set to 0 by program.
8. Change the CM07 bit setting from 0 to 1, after the CM04 bit is set to 1 and the sub clock oscillation stabilizes.
Change the CM07 bit setting from 1 to 0, after the CM05 bit is set to 0 and the main clock oscillation stabilizes.
Do not change the CM07 bit simultaneously with the CM04 or CM05 bit.
9. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to bits CM02, CM05, and CM07 has no effect.
10. When stop mode is entered, the CM03 bit becomes 1.
Figure 9.2 CM0 Register
Rev.1.00 Jul 15, 2007 Page 71 of 352
REJ09B0385-0100