M32C8A Datasheet, PDF (79/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
8. Bus
8.2.4.1 Bus Cycle with Recovery Cycle Inserted
The EWCRi6 bit in the EWCRi register (i = 0 to 3) determines whether the recovery cycle is inserted or not.
Address output or data output is held during the recovery cycle (only when using the separate bus). Devices,
which require longer address hold time or data hold time, are connectable.
- Recovery cycle when separate bus is selected (bus cycle is 1 φ + 2 φ)
BCLK
Recovery cycle
Address
A
Address is held
CSi
(1)
Read data
RD
RD
Write data
WR, WRL, WRH
WD
Data is held
- Recovery cycle when multiplexed bus is selected (bus cycle is 2 φ + 3 φ)
BCLK
Recovery cycle
CSi
(1)
Read data
LA
RD
RD
Write data
LA
WD
Data is held
WR (WRL)
ALE
A: address LA: Latch address RD: Read data WD: Write data
i = 0 to 3
NOTE:
1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.9 Recovery Cycle
Rev.1.00 Jul 15, 2007 Page 62 of 352
REJ09B0385-0100