M32C8A Datasheet, PDF (261/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
Set the SU1HIM bit in the UiSMR2 register (i = 0 to 4) and the SCLKDIV bit in the UiSMR register to values
shown in Table 17.17, and apply a trigger signal to the CTSi pin. Then, the SCLKSTPB bit becomes 1 and a
transmit and receive operation starts. Either the same clock cycle as the external clock or the external clock
cycle divided by two can be selected for the serial clock.
When the SCLKSTPB bit in the UiC1 register is set to 0, a transmission and reception in progress stops
immediately.
Figure 17.31 shows an example of the clock-divided synchronous function.
Table 17.17 Clock-Divided Synchronous Function Select
SCLKDIV bit in the
UiSMR register
SU1HIM bit in the
UiSMR2 register
Clock-Divided Synchronous Function
0
0
Not synchronized
0
1
Same clock cycle as the external clock
1
0 or 1
External clock cycle divided by 2
External clock
from the CLKi pin
Trigger signal input
to the CTSi pin
Serial clock
A
TXDi
More than 1 clock
cycle is required
12345678
12345678
The clock is stopped by the
SCLKSTPB bit in the UiC1 register
Serial clock
B
TXDi
1
2
3
4
5
6
7
8
i = 0 to 4
A: When the SCLKDIV bit in the UiSMR register is set to 0, and the SU1HIM bit in the UiSMR2 register is set to 1
B: When the SCLKDIV bit is set to 1, and SU1HIM bit is set to either 0 or 1.
Figure 17.31 Clock-Divided Synchronous Function
Rev.1.00 Jul 15, 2007 Page 244 of 352
REJ09B0385-0100