M32C8A Datasheet, PDF (237/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
Example of the receive operation timing (1 stop bit)
“H”
RXDi input
“L”
Clock divided by UiBRG
register
(note 1)
Start bit
D0
Verify the level
(note 2)
Input the
receive data
Stop bit
Internal receive clock
1
IR bit in the SiRIC register
0
1
RI bit in the UiC1 register
0
“H”
RTSi output
“L”
The output signal becomes "H"
when the receive operation starts
The output signal becomes "L"
when the RE bit in the UiC1 register
is set to 1
i = 0 to 4
The above applies under the following conditions:
- UiMR register: STPS bit = 0 (1 stop bit)
- UiC0 register: CRS bit = 1 (CTS function not used)
Set to 0 by an interrupt request
acknowledgement or by program
This bit becomes 1 when the data is transferred
from UARTi receive shift register to UiRB register
The RI bit becomes 0 and RTSi output
becomes "L" by reading the UiRB register
NOTES:
1. RXDi input is sampled using the clock divided by the setting value of the UiBRG register. The internal receive
clock is generated after detecting the falling edge of the start bit, and then the receive operation starts.
2. When "L" is detected, the receive operation continues. When "H" is detected, the receive operation is cancelled.
When the receive operatin is cancelled, the RTSi output becomes "L".
Figure 17.19 Receive Operation in UART Mode
Rev.1.00 Jul 15, 2007 Page 220 of 352
REJ09B0385-0100