M32C8A Datasheet, PDF (81/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
8. Bus
- Separate bus (bus cycle is 1φ + 2φ)
BCLK
- Multiplexed bus (bus cycle is 1φ + 2φ)
BCLK
CSi⁽¹⁾
CSi⁽¹⁾
RD
RD
RDY
tsu(RDY-BCLK)
RDY
tsu(RDY-BCLK)
i = 0 to 3
Timing to input RDY signal
Timing to input RDY signal
: Wait states inserted by RDY input
tsu(RDY-BCLK): RDY input setup time
NOTE:
1. Chip-select output (CSi) may be extended depending on the CPU state such as the instruction queue buffer.
Figure 8.11 RD Output Signal Extended by RDY Input
8.2.7 HOLD Input
The HOLD input signal is used to transfer ownership of the bus from the CPU to external devices. When a low-
level (“L”) signal is applied to the HOLD pin, the MCU enters a hold state after the bus access in progress is
completed. While the HOLD pin is held “L”, the MCU remains in a hold state and the HLDA pin outputs an
“L” signal. Table 8.8 lists the MCU states in hold state.
Bus is used in the following priority order: HOLD, DMAC, CPU.
Table 8.8 MCU States in Hold State
Item
Clock generation circuits
CPU
Internal peripheral circuits
RD, WR, A0 to A22, A23, D0 to D15, CS0 to CS3, BHE
HLDA
ALE
Programmable I/O ports
State
Operating (oscillating)
Stopped
Operating
(Watchdog timer is stopped)⁽¹⁾
High-impedance
Outputs “L”
Outputs “L”
Maintains the same state as when “L” is input to HOLD pin.
NOTE:
1. When the PM22 bit in the PM2 register is set to 1 (selects the on-chip oscillator clock as count source for the
watchdog timer), watchdog timer does not stop.
Rev.1.00 Jul 15, 2007 Page 64 of 352
REJ09B0385-0100