M32C8A Datasheet, PDF (226/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
Start initial setting
I flag = 0
UiMR register: bits SMD2 to SMD0 = 001b
CKDIR bit
bits 7 to 4 = 0000b
UiSMR register = 00h
UiSMR2 register = 00h
UiSMR3 register = 00h
UiSMR4 register= 00h
UiC0 register: bits CLK1 and CLK0
CRS bit
CRD bit
NCH bit
CKPOL bit
UFORM bit
<When an internal clock is used>
UiBRG register = m
Interrupt disabled
Clock synchronous mode
Clock select bit
UiBRG register count source select bits
CTS function select bit
CTS function disable bit
Data output select bit
CLK polarity select bit
Bit order select bit
m = 00h to FFh Baud rate =
fj
fj: f1, f8, f2n⁽¹⁾
2(m + 1)
UiC1 register: TE bit = 0
RE bit = 0
UiIRS bit
UiRRM bit
UiLCH bit
Bit 7 = 0
SiTIC register: bits ILVL2 to ILVL0
IR bit = 0
SiRIC register: bits ILVL2 to ILVL0
IR bit= 0
Pin settings in the Function Select Registers
I flag = 1
UiC1 register: TE bit = 1
RE bit = 1
End initial setting
Transmit operation disabled
Receive operation disabled
UARTi transmit interrupt source select bit
Continuous receive mode enable bit⁽²⁾
Data logic select bit
Transmit interrupt priority level select bit
Interrupt not requested
Receive interrupt priority level select bit
Interrupt not requested
Interrupt enabled
Transmit operation enabled
Receive operation enabled
Transmit/receive operation starts by writing data to the UiTB register.
Read the UiRB register when a receive operation is completed.
i = 0 to 4
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. The UiRRM bit can be set to 1 (continuous receive mode used), only when the CKDIR bit in the UiMR register is set to 1
(external clock) and RTS function is disabled.
Figure 17.11 Register Settings in Clock Synchronous Mode
Rev.1.00 Jul 15, 2007 Page 209 of 352
REJ09B0385-0100