M32C8A Datasheet, PDF (150/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
14. DMACII
14. DMACII
DMACII performs memory-to-memory transfer, immediate data transfer, and calculation transfer which transfers a
result of the addition of two data. DMACII transfer occurs in response to interrupt requests from the peripheral
functions.
Table 14.1 lists specifications of DMACII.
Table 14.1 DMACII Specifications
Item
Specification
DMACII request source
Interrupt requests generated by any peripheral functions with bits ILVL2 to ILVL0
in the Interrupt Control Register set to 111b (level 7)
Transfer data
- Data in a memory location is transferred to another memory location
(memory-to-memory transfer)
- Immediate data is transferred to a memory location (immediate data transfer)
- Data in a memory location (or immediate data) + data in another memory location
is transferred to the other memory location (calculation transfer)
Transfer unit
Transfer space
8 bits or 16 bits
64-Kbyte space in addresses 00000h to 0FFFFh⁽¹⁾⁽²⁾
Transfer address
Fixed address: one specified address
Incremented address: address which is incremented by the transfer unit on each
successive access.
(Selectable for source address and destination address individually)
Transfer mode
Single transfer, burst transfer, multiple transfer
Chain transfer function
Address indicated by an interrupt vector for DMACII index is replaced when a
transfer counter reaches zero
End-of-transfer interrupt
Interrupt occurs when a transfer counter reaches zero
NOTES:
1. When a destination address is 0FFFFh and a 16-bit data is transferred, it is transferred to addresses 0FFFFh
and 10000h. Likewise, when a source address is 0FFFFh, a 16-bit data in addresses 0FFFFh and 10000h is
transferred to a given destination address.
2. The actual transferable space varies depending on internal RAM capacity.
14.1 DMACII Settings
Set up the following registers and tables to activate DMACII.
• RLVL register
• DMACII Index
• Interrupt Control Register of the peripheral functions triggering DMACII requests
• The relocatable vector table of the peripheral functions triggering DMACII requests
14.1.1 RLVL Register
When the DMAII bit is set to 1 (interrupt priority level 7 is used for DMACII transfer) and the FSIT bit to 0
(interrupt priority level 7 is used for normal interrupt), DMACII is activated by an interrupt request from any
peripheral functions with bits ILVL2 to ILVL0 in the Interrupt Control Register set to 111b (level 7).
Figure 14.1 shows the RLVL register.
Rev.1.00 Jul 15, 2007 Page 133 of 352
REJ09B0385-0100