M32C8A Datasheet, PDF (255/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
Start initial setting
I flag = 0
UiMR register: bits SMD2 to SMD0 = 001b
CKDIR bit
IOPOL bit = 0
UiSMR register = 00h
UiSMR2 register = 00h
UiSMR3 register: SSE bit = 1
CKPH bit
DINC bit
NODC bit = 0
bits DL2 to DL0 = 000b
UiSMR4 register = 00h
UiC0 register: bits CLK1 to CLK0
CRD bit = 1
NCH bit
CKPOL bit
UFORM bit
< When an internal clock is used >
UiBRG register = m
UiC1 register: TE bit = 0
RE bit = 0
UiIRS bit
UiRRM bit = 0
UiLCH bit = 0
bit 7 = 0
SiTIC register: bits ILVL2 to ILVL0
IR bit = 0
SiRIC register: bits ILVL2 to ILVL0
IR bit = 0
Pin setting in the Function Select Registers
I flag = 1
UiC1 register: TE bit = 1
RE bit = 1
End initial setting
Interrupt disabled
Clock synchronous mode
Clock select bit⁽¹⁾
SS function enabled
Clock phase set bit⁽²⁾
Serial input pin set bit⁽¹⁾
UiBRG count source select bits
CTS function disabled
Data output select bit
CLK polarity select bit⁽²⁾
Bit order select bit
m = 00h to FFh
Baud rate =
fj
2(m + 1)
fj: f1, f8, f2n⁽³⁾
Transmit operation disabled
Receive operation disabled
UARTi transmit interrupt souce select bit
Transmit interrupt priority level select bit
Interrupt not requested
Receive interrupt priority level select bit
Interrupt not requested
Interrupt enabled
Transmit operation enabled
Receive operation enabled
Transmit/receive operation starts by writing data to UiTB register.
Read the UiRB register when the receive operation is completed.
i = 0 to 4
NOTES:
1. Set to 0 in master mode, and set to 1 in slave mode.
2. The clock phase is determined by the combination of the CKPH and CKPOL bits in the UiSMR3 register.
3. Bits CNT3 to CNT0 select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.27 Register Settings in Special Mode 2
Rev.1.00 Jul 15, 2007 Page 238 of 352
REJ09B0385-0100