M32C8A Datasheet, PDF (89/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
9. Clock Generation Circuits
System Clock Control Register 1⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
010000
Symbol
CM1
Address
0007h
Bit Symbol
Bit Name
CM10
All clock stop control bit^{(2, 3, 5)}
−
(b4-b1)
−
(b5)
−
(b6)
Reserved bits
Reserved bit
Reserved bit
CM17
CPU clock select bit 1^{(4, 5)}
Function
0: Clock oscillates
1: All clocks stop (stop mode)
Set to 0
Set to 1
Set to 0
0: Main clock
1: PLL clock
After Reset
0010 0000b
RW
RW
RW
RW
RW
RW
NOTES:
1. Set the CM1 register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. When the CM10 bit is set to 1, the XOUT pin outputs "H" and the built-in feedback resistor is disconnected. Pins XIN, XCIN,
and XCOUT are placed in high-impedance states.
3. When the CM10 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode).
Do not set the CM10 bit to 1, when the CM20 bit in the CM2 register is set to 1 (oscillation stop detect function enabled) or the
CM21 bit in the CM2 register is set to 1 (on-chip oscillator clock selected).
4. Set the CM17 bit to 1 after the PLL clock oscillation stablilizes.
5. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), writes to bits CM10 and CM17 have no effect.
If the PM22 bit in the PM2 register is set to 1 (on-chip oscillator clock as watchdog timer count source), a write to the CM10 bit
has no effect.
Figure 9.3 CM1 Register
Rev.1.00 Jul 15, 2007 Page 72 of 352
REJ09B0385-0100