M32C8A Datasheet, PDF (224/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
17.1.1 Clock Synchronous Mode
Full-duplex clock synchronous serial communications are allowed in this mode. CTS/RTS function can be used
for transmit and receive control.
Table 17.1 lists specifications of clock synchronous mode. Table 17.2 lists pin settings. Figure 17.11 shows
register settings. Figure 17.12 shows an example of a transmit and receive operation when an internal clock is
selected. Figure 17.13 shows an example of a receive operation when an external clock is selected.
Table 17.1 Clock Synchronous Mode Specifications
Item
Specification
Data format
Data length: 8 bits long
Serial clock
Internal clock or external clock can be selected by the CKDIR bit in the UiMR register
(i = 0 to 4)
Baud rate
• When the CKDIR bit is set to 0 (internal clock):
fj / (2 (m + 1)
fj = f1, f8, f2n⁽¹⁾ m: setting value of the UiBRG register (00h to FFh)
• When the CKDIR bit is set to 1 (external clock): clock input to the CLKi pin
Transmit/receive control
Selectable among the CTS function, RTS function, or CTS/RTS function disabled
Transmit and receive
start condition
Internal clock is selected:
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• “L” signal is applied to the CTSi pin when the CTS function is used
External clock is selected⁽²⁾:
• Set the TE bit to 1
• The TI bit is 0
• Set the RE bit to 1
• The RI bit in the UiC1 register is 0 when the RTS function is used
When above 4 conditions are met, RTSi pin outputs “L”
If transmit-only operation is performed, the RE bit setting is not required in both cases.
Interrupt request
generation timing
Error detection
Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following):
• The UiIRS bit is set to 0 (no data in the UiTB register):
when data is transferred from the UiTB register to the UARTi transmit shift register
(transmit operation started)
• The UiIRS bit is set to 1 (transmit operation completed):
when data transmit operation from the UARTi transmit shift register is completed
Receive interrupt:
• When data is transferred from the UARTi receive shift register to the UiRB register
(receive operation completed)
Overrun error⁽³⁾
Overrun error occurs when the 7th bit of the next data is received before
reading the UiRB register
Selectable function
• CLK polarity
Transmit data output timing and receive data input timing can be selected
• LSB first or MSB first
Data is transmitted and received from either bit 0 or bit 7
• Serial data logic inverse
Transmit and receive data are logically inverted
• Continuous receive mode
The TI bit becomes 0 by reading the UiRB register
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an external clock is selected, ensure that an “H” signal is applied to the CLKi pin when the CKPOL bit in the
UiC0 register is set to 0, and that an “L” signal is applied when the CKPOL bit is set to 1.
3. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
register remains unchanged as 0 (interrupt not requested).
Rev.1.00 Jul 15, 2007 Page 207 of 352
REJ09B0385-0100