M32C8A Datasheet, PDF (272/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
18. A/D Converter
A/D0 Control Register 1⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AD0CON1
Address
0397h
After Reset
00h
Bit Symbol
Bit Name
Function
RW
Single sweep mode and repeat sweep mode 0
b1 b0
SCAN0
0 0: ANi_0, ANi_1 (i = none, 15)
0 1: ANi_0 to ANi_3
RW
1 0: ANi_0 to ANi_5
1 1: ANi_0 to ANi_7
Repeat sweep mode 1⁽³⁾
A/D Sweep pin select bits⁽²⁾
b1 b0
0 0: ANi_0
0 1: ANi_0, ANi_1
1 0: ANi_0 to ANi_2
SCAN1
1 1: ANi_0 to ANi_3
RW
Multi-port single sweep mode and multi-port
repeat sweep mode 0⁽⁴⁾
Set to 11b.
MD2
A/D operating mode
select bit 1⁽⁴⁾
0: Other than repeat sweep mode 1
1: Repeat sweep mode 1
RW
BITS
Resolution select bit
0: 8-bit mode
1: 10-bit mode
RW
CKS1
Frequency select bit 1
(Note 5)
RW
VCUT
VREF connection bit⁽⁸⁾
OPA0
OPA1
Extended input pin function
select bits^{(4, 6)}
0: VREF not connected⁽⁷⁾
1: VREF connected
RW
b7 b6
RW
0 0: ANEX0 and ANEX1 are not used
0 1: Signal applied to ANEX0 is A/D converted
1 0: Signal applied to ANEX1 is A/D converted
1 1: External op-amp connection
RW
NOTES:
1. If the AD0CON1 register is rewritten during A/D conversion, the conversion result will be incorrect.
2. Bits SCAN1 and SCAN0 are enabled in single sweep mode, repeat sweep mode 0, 1, multi-port single sweep mode, and multi-
port repeat sweep mode 0.
3. These are prioritized pins used for A/D conversion when the MD2 bit is set to 1.
4. When the MSS bit in the AD0CON3 register is set to 1 (multi-port sweep mode used);
-set bits SCAN1 and SCAN0 to 11b
-set the MD2 bit to 0
-set bits OPA1 and OPA0 to 00b.
5. Refer to the note for the CKS0 bit in the AD0CON0 register.
6. Bits OPA1 and OPA0 can be set to 01b or 10b in one-shot mode and repeat mode. Set these bits to 00b or 11b in other
modes.
7. Do not set the VCUT bit to 0 during A/D conversion. Even if the VCUT bit is set to 0, VREF remains connected to the D/A
converter.
8. When the VCUT bit is set to 1 from 0, wait for 1 μs or more to start the A/D conversion.
Figure 18.3 AD0CON1 Register
Rev.1.00 Jul 15, 2007 Page 255 of 352
REJ09B0385-0100