M32C8A Datasheet, PDF (165/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
15. Timers (Timer A)
Timer Ai Mode Register (i = 0 to 4)(Pulse Width Modulation Mode)
b7 b6 b5 b4 b3 b2 b1 b0
011
Symbol
TA0MR to TA4MR
Address
0356h, 0357h, 0358h, 0359h, 035Ah
After Reset
00h
Bit Symbol
Bit Name
Function
RW
TMOD0
RW
Operating mode select bits
b1 b0
1 1: Pulse width modulation (PWM) mode
TMOD1
RW
−
(b2)
Reserved bit
Set to 0
RW
MR1
MR2
MR3
External trigger select bit⁽¹⁾
0: Falling edge of signal applied to the TAiIN pin
RW
1: Rising edge of signal applied to the TAiIN pin
Trigger select bit
0: The TAiS bit is enabled
RW
1: Selected by bits TAiTGH and TAiTGL
16/8-bit PWM mode select bit
0: Functions as 16-bit pulse width modulator
1: Functions as 8-bit pulse width modulator
RW
TCK0
b7 b6
RW
0 0: f1
Count source select bits
0 1: f8
1 0: f2n ⁽²⁾
TCK1
RW
1 1: fC32
NOTES:
1. The MR1 bit is enabled only when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are set to 00b (input to the TAiIN
pin).
The MR1 bit can be set to either 0 or 1 when bits TAiTGH and TAiTGL are set to 01b (TB2 overflow or underflow), 10b (TAj
(j = i - 1, except j = 4 if i = 0) overflow or underflow), or 11b (TAk (k = i + 1, except i = 4 if k = 0) overflow or underflow).
2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the
CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.8 TA0MR to TA4MR Registers in Pulse Width Modulation Mode
Rev.1.00 Jul 15, 2007 Page 148 of 352
REJ09B0385-0100