M32C8A Datasheet, PDF (85/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
8. Bus
8-bit data bus width
BCLK
3φ + 3φ
Set using bits EWCR34 to EWCR30
Set using bits PWCR106 to PWCR104
1φ + 2φ 1φ + 2φ
1φ + 2φ
3φ + 3φ
1φ + 2φ
Address
FFF000h
FFF001h FFF002h
FFF007h
FFF008h
FFF009h
Data
CS0 (CE)
RD (OE)
The above applies under the following conditions:
- Bits PM11 and PM10 in the PM1 register are set to 11b (mode 3).
- The DS3 bit in the DS regiter is set to 0 (8 bits wide).
- Bits EWCR34 to EWCR30 in the EWCR3 register are set to 10011b (3 φ + 3φ).
- The EWCR36 bit is set to 0 (add no recovery cycle when accessing external space 3).
- Bits PWCR106 to PWCR104 are set to 010b (1φ + 2φ).
- The PWCR107 bit is set to 1 (page mode control enabled).
If the MCU accesses data in other than the eight-byte block of consecutive addresses, the page mode controlled access
is started over from the first bus access.
16-bit data bus width
BCLK
3φ + 3φ
Set using bits EWCR34 to EWCR30
Set using bits PWCR106 to PWCR104
1φ + 2φ 1φ + 2φ 1φ + 2φ
3φ + 3φ
1φ + 2φ 1φ + 2φ
Address
FFF000h
FFF002h FFF004h FFF006h
FFF008h
FFF00Ah FFF00Ch
Data
CS0 (CE)
RD (OE)
The above applies under the following conditions:
- Bits PM11 and PM10 in the PM1 register are set to 11b (mode 3).
- The DS3 bit in the DS regiter is set to 1 (16 bits wide).
- Bits EWCR34 to EWCR30 in the EWCR3 register are set to 10011b (3 φ + 3φ).
- The EWCR36 bit is set to 0 (add no recovery cycle when accessing external space 3).
- Bits PWCR106 to PWCR104 are set to 010b (1φ + 2φ).
- The PWCR107 bit is set to 1 (page mode control enabled).
Figure 8.14 External Bus Timing with Page Mode Control Function
Rev.1.00 Jul 15, 2007 Page 68 of 352
REJ09B0385-0100