M32C8A Datasheet, PDF (227/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
Internal clock
TE bit in the
1
UiC1 register
0
TI bit in the UiC1
1
register
0
“H”
CTSi Input
“L”
“H”
CLKi output
“L”
“H”
TXDi output
“L”
TXEP bit in the
1
UiC0 register
0
IR bit in the
1
SiTIC register
0
TC
Write data to the UiTB register
Transfer data from UiTB register
to UARTi transmit shift register
TCLK
Communication stops
because CTSi = "H"
Communication stops because
TE bit = 0
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Set to 0 by an interrupt request acknowledgement or by program
“H”
RXDi input
“L”
RI bit in the
1
UiC1 register
0
IR bit in the SiRIC ¹
register
0
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Transfer data from UARTi
receive shift register to UiRB
register
A read from the UiRB register
D0 D1 D2 D3 D4 D5
Set to 0 by an interrupt request acknowlegement or by program
i = 0 to 4
TC = TCLK = ^{2(m + 1)}
fj
The above applies under the following conditions:
fj = f1, f8, f2n⁽¹⁾
- UiMR register: CKDIR bit = 0 (internal clock)
m = Setting value of the UiBRG register
- UiC0 register: CRD bit in the = 0 and CRS bit = 0 (CTS function used)
(00h to FFh)
CKPOL bit = 0 (transmit data output at the falling edge of the serial clock)
- UiC1 register: UiIRS bit = 0 (Transmit interrupt request is generated when no data in the UiTB register)
NOTE:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.12 Transmit and Receive Operations when Internal Clock is Selected
Rev.1.00 Jul 15, 2007 Page 210 of 352
REJ09B0385-0100