M32C8A Datasheet, PDF (127/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
High
Interrupt priority level
DMA0
DMA1
DMA2
DMA3
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
UART0 transmission/NACK
UART0 reception/ACK
UART1 transmission/NACK
UART1 reception/ACK
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
INT5
INT4
INT3
INT2
INT1
INT0
Timer B5
UART2 transmission/NACK
UART2 reception/ACK
UART3 transmission/NACK
UART3 reception/ACK
UART4 transmission/NACK
UART4 reception/ACK
Bus conflict/
start or stop condition detection
Low
(UART2)
Peripheral function interrupt priority
(if priority levels are the same)
Level 0 (initial value)
Interrupt priority level
Bus conflict/
start or stop condition detection
(UART0, UART3)
Bus conflict/
start or stop condition detection
(UART1, UART4)
A/D0
Key input interrupt
Bits RLVL2 to RLVL0
IPL
I flag
Address match
Watchdog timer,
oscillation stop detection,
Vdet4 detection
NMI
DMACII
Figure 11.10 Interrupt Priority Level Select Circuit
Rev.1.00 Jul 15, 2007 Page 110 of 352
REJ09B0385-0100
11. Interrupts
Interrupt request priority
level detection result outputs
(to the clock generation
circuit)
Interrupt request
acknowledged
(to CPU)