M32C8A Datasheet, PDF (233/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
17.1.2 Clock Asynchronous (UART) Mode
Full-duplex asynchronous serial communications are allowed in this mode. Table 17.3 lists specifications of
UART mode. Table 17.4 lists pin settings. Figure 17.17 shows register settings. Figure 17.18 shows an
example of a transmit operation. Figure 17.19 shows an example of a receive operation.
Table 17.3 UART Mode Specifications
Item
Specification
Data format
Baud rate
• Data length: selectable among 7 bits, 8 bits, or 9 bits long
• Start bit: 1 bit long
• Parity bit: selectable among odd, even, or none
• Stop bit: selectable from 1 bit or 2 bits long
fj / (16 (m + 1))
fj = f1, f8, f2n⁽¹⁾, fEXT
m: setting value of the UiBRG register (00h to FFh)
fEXT: clock input to the CLKi pin when the CKDIR bit in the UiMR register is
set to 1 (external clock)
Transmit/receive control
Selectable among CTS function, RTS function or CTS/RTS function disabled
Transmit start condition
To start transmit operation, all of the following must be met:
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
• Apply a low-level (“L”) signal to the CTSi pin when the CTS function is selected
Receive start condition
To start receive operation, all of the following must be met:
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• The RI bit is 1 (no data in UiRB register) when RTS function is used.
When the above two conditions are met, the RTSi pin output an “L” signal.
• The start bit is detected
Interrupt request generation
timing
Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following):
• The UiIRS bit is set to 0 (no data in the UiTB register):
when data is transferred from the UiTB register to the UARTi transmit shift register
(transmit operation started)
• The UiIRS bit is set to 1 (transmit operation completed):
when the final stop bit is output from the UARTi transmit shift register
Receive interrupt:
• When data is transferred from the UARTi receive shift register to the UiRB register
(receive operation completed)
Error detection
• Overrun error⁽²⁾
Overrun error occurs when the preceding bit of the final stop bit of the next data (the
first stop bit when selecting 2 stop bits) is received before reading the UiRB register
• Framing error
Framing error occurs when the number of the stop bits set by the STPS bit in
the UiMR register is not detected
• Parity error
Parity error occurs when parity is enabled and the received data does not have
the correct even or odd parity set by the PRY bit in the UiMR register.
• Error sum flag
Error sum flag is set to 1 when any of overrun, framing, and parity errors occurs
Selectable function
• LSB first or MSB first
Data is transmitted or received from either bit 0 or bit 7
• Serial data logic inverse
Transmit and receive data are logically inverted. The start bit and stop bit are
not inverted
• TXD and RXD I/O polarity inverse
The level output from the TXD pin and the level applied to the RXD pin are
inverted. All the data including the start bit and stop bit are inverted.
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
register remains unchanged as 0 (interrupt not requested).
Rev.1.00 Jul 15, 2007 Page 216 of 352
REJ09B0385-0100