M32C8A Datasheet, PDF (185/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
15. Timers (Timer B)
Timer Bi Mode Register (i = 0 to 5)(Event Counter Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol
TB0MR to TB5MR
Address
035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh
Bit Symbol
Bit Name
Function
After Reset
00XX 0000b
RW
TMOD0
RW
Operating mode select bits
b1 b0
0 1: Event counter mode
TMOD1
RW
MR0
MR1
Count polarity select bits⁽¹⁾
b3 b2
0 0: Falling edges of an external signal counted
RW
0 1: Rising edges of an external signal counted
1 0: Falling and rising edges of an external
signal counted
RW
1 1: Do not set to this value
Registers TB0MR and TB3MR:
Set to 0 in event counter mode.
RW
MR2
Registers TB1MR, TB2MR, TB4MR, and TB5MR:
Unimplemented.
−
Write 0. Read as undefined value.
MR3
Disabled in event counter mode.
Write 0. Read as undefined value.
−
TCK0
Disabled in event counter mode.
Can be set to either 0 or 1
RW
TCK1
Event clock select bit
0: Signal applied to the TBiIN pin
1: TBj overflows or underflows⁽²⁾
RW
NOTES:
1. Bits MR1 and MR0 are enabled when the TCK1 bit is set to 0. Bits MR1 and MR0 can be set to either 0 or 1 when the TCK1 bit
is set to 1.
2. j = i - 1, except j = 2 if i = 0 and j = 5 if i = 3.
Figure 15.23 TB0MR to TB5MR Registers in Event Counter Mode
Rev.1.00 Jul 15, 2007 Page 168 of 352
REJ09B0385-0100