M32C8A Datasheet, PDF (148/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
13. DMAC
13.2 DMA Transfer Time
The DMA transfer time can be calculated as follows. (in terms of bus clock)
Table 13.3 lists the number of the source read cycle and destination write cycle. Table 13.4 lists coefficient j, k (the
number of bus clock).
Transfer time = source read bus cycle × j + destination write bus cycle × k
Table 13.3 Source Read Cycle and Destination Write Cycle
Transfer Unit
Bus Width
Access
Address
Accessing Internal Space
Read Cycle Write Cycle
8-bit transfer
16 bits
(BWi bit in the DMDp
register = 0)
8 bits
Even
Odd
Even
1
1
1
1
−
−
Odd
−
−
16-bit transfer
(BWi bit = 1)
16 bits
Even
Odd
1
1
2
2
8 bits
Even
−
−
Odd
−
−
i=0 to 3, p=0 and 1
Accessing External Space
Read Cycle Write Cycle
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
Table 13.4 Coefficient j, k
Internal Space
Internal RAM
Internal RAM
with no wait state
j=1
k=1
with wait state
j=2
k=2
SFR area
j=2
k=2
External Space
j and k BCLK cycles shown in Table 8.6 (j, k = 2 to 9).
Add one cycle to j or k cycles when inserting a recovery
cycle
13.3 Channel Priority and DMA Transfer Timing
When multiple DMA requests are generated in the same sampling period (between a falling edge of the BCLK and
the next falling edge), the corresponding DRQ bits in the DMiSL register (i = 0 to 3) are set to 1 (requested)
simultaneously. Channel priority in this case is: DMA0 > DMA1 > DMA2 > DMA3. Leave the following period
between each DMA transfer request generation on the same channel.
DMA request interval ≥ (number of channels set for DMA transfer - 1) × 5 BCLK cycles
Described in the following is the operation when DMA0 and DMA1 requests are generated in the same sampling
period. Figure 13.9 shows an example of DMA transfers triggered by the INT interrupts.
In Figure 13.9, DMA0 and DMA1 requests are generated simultaneously. A DMA0 request having higher priority
is acknowledged first to start a transfer. After one DMA0 transfer is completed, the DMAC returns ownership of
the bus to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1
transfer is completed, bus ownership is again returned to the CPU.
DMA requests cannot be counted up since each channel has one DRQ bit. Even if multiple DMA1 requests are
generated before receiving bus ownership as shown in Figure 13.9, the DRQ bit is set to 0 as soon as bus ownership
is acquired. Bus ownership is returned to the CPU after one transfer is completed.
Rev.1.00 Jul 15, 2007 Page 131 of 352
REJ09B0385-0100