M32C8A Datasheet, PDF (243/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
Table 17.7
Register
UiMR
UiSMR
UiSMR2
UiSMR3
UiSMR4
i = 0 to 4
Register Settings in I²C Mode (1)
Setting Value
Bit
Master
Slave
SMD2 to SMD0
Set to 010b
CKDIR
Set to 0
Set to 1
IOPOL
Set to 0
IICM
Set to 1
ABC
Select an arbitration lost detect timing Disabled
BBS
Bus busy flag
7 to 3
IICM2
Set to 00000b
See Table 17.9 and 17.10 Functions in I²C Mode
CSC
Set to 1 to enable clock
synchronization
Set to 0
SWC
Set to 1 to hold an “L” signal output from SCLi at the falling edge of the ninth
bit of the serial clock
ALS
Set to 1 to abort an SDAi output when Set to 0
detecting the arbitration lost
STC
Set to 0
Set to 1 to initialize UARTi by
detecting the start condition
SWC2
Set to 1 to forcibly make a signal output from SCL an “L”
SDHI
Set to 1 to disable SDA output
SU1HIM
Set to 0
SSE
CKPH
Set to 0
See Table 17.9 and 17.10 Functions in I²C Mode
DINC, NODC, ERR Set to 0
DL2 to DL0
Set SDAi digital delay value
STAREQ
Set to 1 to generate the start
condition
Set to 0
RSTAREQ
Set to 1 to generate the restart
condition
STPREQ
Set to 1 to generate the stop
condition
STSPSEL
Set to 1 when using a condition
generation function
ACKD
Select ACK or NACK
ACKC
Set to 1 to output ACK data
SCLHI
Set to 1 to enable SCL output stop Set to 0
when detecting the stop condition
SWC9
Set to 0
Set to 1 to hold an “L” signal output
from SCLi at the falling edge of the
ninth bit of the serial clock
Rev.1.00 Jul 15, 2007 Page 226 of 352
REJ09B0385-0100