M32C8A Datasheet, PDF (271/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
18. A/D Converter
A/D0 Control Register 0⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AD0CON0
Address
0396h
After Reset
00h
Bit Symbol
Bit Name
CH0
CH1
CH2
Analog input pin
select bits^{(2, 3)}
MD0
A/D operating mode
select bits 0⁽²⁾
MD1
TRG
Trigger select bit
ADST
A/D conversion start bit
Function
RW
b2 b1 b0
0 0 0: ANi_0
RW
0 0 1: ANi_1
0 1 0: ANi_2
0 1 1: ANi_3
RW
1 0 0: ANi_4
1 0 1: ANi_5
1 1 0: ANi_6
1 1 1: ANi_7 (i = none, 15)
RW
When the MSS bit in the AD0CON3 register = 0
b4 b3
0 0: One-shot mode
RW
0 1: Repeat mode
1 0: Single sweep mode
1 1: Repeat sweep mode 0, repeat sweep mode 1
When the MSS bit in the AD0CON3 register = 1
b4 b3
0 0:
0 1:
Do not set to these values.
RW
1 0: Multi-port single sweep mode
1 1: Multi-port repeat sweep mode 0
0: Software trigger
1: External trigger, hardware trigger⁽⁴⁾
RW
0: A/D conversion stops
1: A/D conversion starts⁽⁴⁾
RW
CKS0
Frequency select bit 0
(Note 5)
RW
NOTES:
1. If the AD0CON0 register is rewritten during A/D conversion, the conversion result will be incorrect.
2. Analog input pins must be configured again after an A/D operating mode is changed.
3. Bit CH2 to CH0 is enabled in one-shot mode and repeat mode.
4. To set the TRG bit to 1, select a trigger source using the TRG0 bit in the AD0CON2 register. Then, set the ADST bit to 1 after
the TRG bit is set to 1.
5. φAD frequency must be 16 MHz or below when VCC1 = 4.2 to 5.0V.
φAD frequency must be 10 MHz or below when VCC1 = 3.0 to 5.0V.
φAD is selected by the combination of the CKS0 bit, the CKS1 in the AD0CON1 register, and the CKS2 bit in the AD0CON3
register.
CKS2 bit
in AD0CON3 register
CKS0 bit
in AD0CON0 register
CKS1 bit
in AD0CON1 register
φAD
0
fAD divided by 4
0
1
fAD divided by 3
0
0
fAD divided by 2
1
1
fAD
0
fAD divided by 8
1
0
1
fAD divided by 6
Figure 18.2 AD0CON0 Register
Rev.1.00 Jul 15, 2007 Page 254 of 352
REJ09B0385-0100