M32C8A Datasheet, PDF (163/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
15. Timers (Timer A)
Timer Ai Mode Register (i = 0 to 4)(Event Counter Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol
TA0MR to TA4MR
Address
0356h, 0357h, 0358h, 0359h, 035Ah
After Reset
00h
Bit Symbol
Bit Name
Function
Function
(When not processing
(When processing
RW
two-phase pulse signals)
two-phase pulse signals)
TMOD0
RW
Operating mode select bits
b1 b0
0 1: Event counter mode⁽¹⁾
TMOD1
RW
−
(b2)
Reserved bit
Set to 0
RW
0: Falling edges of an
MR1
Count polarity select bit⁽²⁾
external signal counted _{Set to 0}
RW
1: Rising edges of an
external signal counted
MR2
Increment/decrement
switching source select bit
0: UDF registser setting
1: Signal applied to the
TAiOUT pin⁽³⁾
Set to 1
RW
MR3
Set to 0 in event counter mode
RW
TCK0
TCK1
Count operation type
select bit
Two-phase pulse signal
processing operation
select bit^(4,5)
0: Reload
1: Free running
Set to 0
RW
0: Normal processing
operation
1: Multiply-by-4
RW
processing operation
NOTES:
1. Bits TAiTGH and TAiTGL in the ONSF or TRGSR register determine a count source in event counter mode.
2. The MR1 bit is enabled only when counting external signals.
3. The counter decrements when an "L" signal is applied to the TAiOUT pin. The counter increments when an "H" signal is applied
to the TAiOUT pin.
4. The TCK1 bit is enabled only in the TA3MR register. The TCK1 bit in registers TA0MR to TA2MR and TA4MR are disabled.
5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j = 2 to 4) to 1 (two-phase pulse signal processing
function enabled). Also, set bits TAjTGH and TAjTGL in the TRGSR register to 00b (input to the TAjIN pin).
Figure 15.6 TA0MR to TA4MR Registers in Event Counter Mode
Rev.1.00 Jul 15, 2007 Page 146 of 352
REJ09B0385-0100