English
Language : 

M32C8A Datasheet, PDF (245/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series
M32C/8A Group
17. Serial Interfaces
As shown in Table 17.9, I2C mode is entered when bits SMD2 to SMD0 in the UiMR register are set to 010b
(I2C mode) and the IICM bit in the UiSMR register to 1 (I2C mode). Because an SDAi transmit output passes
through a delay circuit, output signal from the SDAi pin changes after the SCLi pin level becomes low (“L”)
and the “L” output stabilizes.
Table 17.9 Functions in I2C Mode (1)
Function
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/receive interrupt)
CKPH = 0
(no clock delay)
CKPH = 1
(clock delay)
CKPH = 0
(no clock delay)
CKPH = 1
(clock delay)
Interrupt source for
numbers 39 to 41(1)
(See Figure 17.24)
Start condition or stop condition detection
(See Table 17.12 STSPSEL Bit Function)
Interrupt source for
numbers 17, 19, 33, 35,
37(1)
(See Figure 17.24)
No acknowledgement detection (NACKi) -
at the rising edge of 9th bit of SCLi
UARTi transmit
operation - at the
rising edge of 9th bit
of SCLi
UARTi transmit
operation - at the
next falling edge after
the 9th bit of SCLi
Interrupt source for
numbers 18, 20, 34, 36,
38(1)
(See Figure 17.24)
Acknowledgement detection (ACKi) -
at the rising edge of 9th bit of SCLi
UARTi receive operation - at the falling edge
of 9th bit of SCLi
Data transfer timing
from the UART receive
shift register to the UiRB
register
At rising edge of 9th bit of SCLi
Falling edge of 9th bit Falling edge and
of SCLi
rising edge of 9th bit
of SCLi
UARTi transmit output Delay
delay
Functions of P6_3,
P6_7, P7_0, P9_2,
P9_6
Functions of P6_2,
P6_6, P7_1, P9_1,
P9_7
SDAi input and output
SCLi input and output
Noise filter width
200 ns
i = 0 to 4
NOTE:
1. Use the following procedures to change an interrupt source.
(a) Disable an interrupt of the corresponding interrupt number.
(b) Change an interrupt source.
(c) Set the IR bit of a corresponding interrupt number to 0 (interrupt not requested).
(d) Set bits ILVL2 to ILVL0 of the corresponding interrupt number.
Rev.1.00 Jul 15, 2007 Page 228 of 352
REJ09B0385-0100