M32C8A Datasheet, PDF (204/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
16. Three-Phase Motor Control Timer Function
Timer Ai, Ai1 Register^{(1, 2, 3, 4, 5)} (i = 1, 2, 4)
b15
b8 b7
b0
Symbol
TA1, TA2, TA4
TA11, TA21, TA41
Address
0349h - 0348h, 034Bh - 034Ah, 034Fh - 034Eh
0303h - 0302h, 0305h - 0304h, 0307h - 0306h
After Reset
Undefined
Undefined
Function
If a setting value is n, f1 is counted n times after a start trigger
occurs, and then the timer stops. Output signal level for each
phase changes when timers A1, A2, or A4 stop.
Setting Range
RW
0000h to FFFFh
WO
NOTES:
1. Write these registers in 16-bit units. Read-modify-write instructions cannot be used to set registers TAi and TAi1. Refer to
Usage Notes for details.
2. If the TAi or TAi1 register is set to 0000h, the counter does not start and the timer Ai interrupt is not generated.
3. When the INV15 bit in the INVC1 register is set to 0 (dead timer enabled), an output signal is switched to its active level with
delay simultaneously with the dead time timer underflow.
4. When the INV11 bit is set to 0 (Timers A11, A21, and A41 are not used (three-phase mode 0)), the contents of the TAi register
are transferred to the reload register by a timer Ai start trigger. When the INV11 bit is set to 1 (Timers A11, A21, and A41 are
used (three-phase mode 1)), the contents of the TAi1 register are transferred by the first timer Ai start trigger, and then contents
of the TAi register are transferred by the next timer Ai start trigger. Subsequently, the contents of registers TAi1 and TAi are
transferred alternately to the reload register by each timer Ai start trigger.
5. Do not set registers TAi and TAi1 in the timer B2 underflow timing.
Three-Phase Output Buffer Register i⁽¹⁾ (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IDB0, IDB1
Address
030Ah, 030Bh
After Reset
XX11 1111b
Bit Symbol
Bit Name
Function
RW
DUi
DUBi
DVi
Upper arm (U-phase)
output buffer i
Lower arm (U-phase)
output buffer i
Upper arm (V-phase)
output buffer i
Set output levels of the three-phase output shift
registers. The set value is reflected in each
RW
turn-on signal as follows:
0: Active (ON)
RW
1: Inactive (OFF)
When read, the contents of the three-phase
output shift registers are returned.
RW
DVBi
Lower arm (V-phase)
output buffer i
RW
DWi
Upper arm (W-phase)
output buffer i
RW
DWBi
Lower arm (W-phase)
output buffer i
RW
−
(b7-b6)
Unimplemented.
Write 0. Read as undefined value.
−
NOTE:
1. When values are written to registers IDB0 and IDB1, these values are transferred to the three-phase output shift registers by a
transfer trigger. The value written in the IDB0 register becomes the initial output level of each phase when the transfer trigger occurs.
The value written in the IDB1 register becomes the next output signal level when the falling edge of the timer A1, A2 and A4 one-shot
pulses is detected.
Figure 16.9 TA1, TA2, TA4, TA11, TA21, and TA41 Registers, IDB0, IDB1 Registers
Rev.1.00 Jul 15, 2007 Page 187 of 352
REJ09B0385-0100