M32C8A Datasheet, PDF (212/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
16. Three-Phase Motor Control Timer Function
16.3 Short Circuit Prevention Features
16.3.1 Prevention Against Upper/Lower Arm Short Circuit by Program Errors
This function prevents the upper and lower arm short circuit caused by setting the upper and lower output
buffers in registers IDB0 and IDB1 to active simultaneously by program errors and so on.
To use this function, set the INV04 bit in the INVC0 register to 1 (simultaneous turn-on signal output disabled).
If any pair of output buffers (U and U, V and V, or W and W) are simultaneously set to active, the INV05 bit
becomes 1 (detected), and the INV03 bit becomes 0 (three-phase motor control timer output disabled). Then,
the port outputs are forcibly cutoff and the pins are placed in the high-impedance states. When this prevention
function is performed, set the registers associated with the three-phase motor control timer function again.
16.3.2 Arm Short Circuit Prevention Using Dead Time Timer
The dead time timer prevents arm short circuit caused by turn-off delay of external upper and lower transistors.
To enable the dead time timer, set the INV15 bit in the INVC1 register to 0 (dead time enabled). The count
source for dead time timer (fDT) can be selected using the INV12 bit, and the dead time can be set using the
DTT register.
The dead time is obtained from the following formulas.
1
× n (INV12 = 0)
f1
2
× n (INV12 = 1)
f1
n: Value in the DTT register
Figure 16.15 shows an example of dead time timer operation.
U-phase output signal
(internal signal)
U-phase output signal
(internal signal)
Dead time timer
OFF
ON
ON
OFF
Dead timer
OFF
ON
Dead time
U-phase turn-on
signal output
U-phase turn-on
signal output
OFF
ON
ON
OFF
OFF
ON
Figure 16.15 Dead Time Timer Operation
16.3.3 Forced-Cutoff Function by the NMI Input
When an “L” signal is input to the NMI pin, the INV03 bit in the INVC0 register becomes 0 (three-phase motor
control timer output disabled), the port outputs are forcibly cutoff, and then the pins are placed in the high-
impedance states. Also, the NMI interrupt occurs at the same time.
To enable the three-phase motor control timer function after the forced cutoff is performed, set the registers
associated with the three-phase motor control timer function again while an “H” signal is input to the NMI pin.
Forced-cutoff function by the NMI input can be used when the INV02 bit in the INVC0 register is set to 1
(three-phase motor control timer function used) and the INV03 bit is set to 1 (three-phase motor control timer
output enabled).
Rev.1.00 Jul 15, 2007 Page 195 of 352
REJ09B0385-0100