M32C8A Datasheet, PDF (216/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
UARTi Special Mode Register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0SMR to U2SMR
U3SMR, U4SMR
Address
0367h, 02E7h, 0337h
0327h, 02F7h
After Reset
00h
00h
Bit Symbol
Bit Name
Function
RW
IICM
I²C mode select bit
0 : Other than I²C mode
1 : I²C mode
RW
ABC
Arbitration lost detect flag
control bit⁽¹⁾
0: Updated per bit
1: Updated per byte
RW
BBS
Bus busy flag^{(1, 2)}
0: Stop condition detected (bus is free)
1: Start condition detected (bus is busy)
RW
−
(b3)
Reserved bit
Set to 0
RW
ABSCS
Bus conflict detect
sampling clock select bit⁽³⁾
0: Rising edge of serial clock
1: Timer Aj underflow (j = 0, 3, 4)⁽⁴⁾
RW
ACSE
Auto clear function select
bit for transmit enable bit⁽³⁾
0: No auto clear function
1: Auto cleared when bus conflict occurs
RW
SSS
Transmit start condition
select bit⁽³⁾
0 : Not related to RXDi
1 : Synchronized with RXDi
RW
SCLKDIV
Clock division synchronous
bit^(5,6)
0: External clock not divided
1: External clock divided by 2
RW
NOTES:
1. These bits are used in I²C mode.
2. The BBS bit is set to 0 by writing a 0. Writing a 1 has no effect.
3. These bits are used in IE mode.
4. UART0: Timer A3 underflow signal, UART1: Timer A4 underflow signal,
UART2: Timer A0 underflow signal, UART3: Timer A3 underflow signal,
UART4: Timer A4 underflow signal.
5. The SCLKDIV bit is used in GCI mode.
6. Refer to the note for the SU1HIM bit in the UiSMR2 register.
Figure 17.3 U0SMR to U4SMR Registers
Rev.1.00 Jul 15, 2007 Page 199 of 352
REJ09B0385-0100