M32C8A Datasheet, PDF (239/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
17.1.2.3 Serial Data Logic Inverse
When the UiLCH bit in the UiC1 register is set to 1 (inverted), data logic written in the UiTB register is inverted
for transmit operation. A read from the UiRB register returns the inverted logic of receive data. This function
can be used when data length is 7 bits or 8 bits long. Figure 17.21 shows an example of serial data logic inverse
operation.
(1) When the UiLCH bit in the UiC1 register (i = 0 to 4) is set to 0 (not inverted)
TXDi ^"H"
(not inverted) _"L"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
(2) When the UiLCH bit is set to 1 (inverted)
TXDi ^"H"
(inverted) _"L"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
The above applies under the following conditions:
- UiC0 register: UFROM bit = 0 (LSB first)
- UiMR register: STPS bit = 0 (1 stop bit)
PRYE bit = 1 (parity enabled).
Figure 17.21 Serial Data Logic Inverse
17.1.2.4 TXD and RXD I/O Polarity Inverse
The level output from the TXD pin and the level applied to the RXD pin are inverted with this function. When
the IOPOL bit in the UiMR register (i = 0 to 4) is set to 1 (inverted), all the input/output data levels, including
the start bit, stop bit and parity bit, are inverted. Figure 17.22 shows TXD and RXD I/O polarity inverse.
(1) When the IOPOL bit in the UiMR register (i = 0 to 4) is set to 0 (not inverted)
TXDi "H"
(not inverted) _"L"
RXDi "H"
(not inverted) _"L"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
(2) When the IOPOL bit is set to 1 (inverted)
TXDi "H"
(inverted) _"L"
RXDi "H"
(inverted) _"L"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
The above applies under the following conditions:
- UiC0 register: UFORM bit = 0 (LSB first)
- UiMR register: STPS bit = 0 (1 stop bit)
PRYE bit = 1 (parity enabled)
ST: Start bit
P: Parity bit
SP: Stop bit
Figure 17.22 TXD and RXD I/O Polarity Inverse
Rev.1.00 Jul 15, 2007 Page 222 of 352
REJ09B0385-0100